[llvm-commits] [llvm] r142542 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp test/CodeGen/X86/sse2-blend.ll
Devang Patel
dpatel at apple.com
Wed Oct 19 14:24:34 PDT 2011
On Oct 19, 2011, at 1:43 PM, Nadav Rotem wrote:
> Author: nadav
> Date: Wed Oct 19 15:43:16 2011
> New Revision: 142542
>
> URL: http://llvm.org/viewvc/llvm-project?rev=142542&view=rev
> Log:
> Improve code generation for vselect on SSE2:
> When checking the availability of instructions using the TLI, a 'promoted'
> instruction IS available. It means that the value is bitcasted to another type
> for which there is an operation. The correct check for the availablity of an
> instruction is to check if it should be expanded.
>
>
> Modified:
> llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
> llvm/trunk/test/CodeGen/X86/sse2-blend.ll
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp?rev=142542&r1=142541&r2=142542&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp Wed Oct 19 15:43:16 2011
> @@ -394,10 +394,12 @@
>
> // If we can't even use the basic vector operations of
> // AND,OR,XOR, we will have to scalarize the op.
> - if (!TLI.isOperationLegalOrCustom(ISD::AND, VT) ||
> - !TLI.isOperationLegalOrCustom(ISD::XOR, VT) ||
> - !TLI.isOperationLegalOrCustom(ISD::OR, VT))
> - return DAG.UnrollVectorOp(Op.getNode());
> + // Notice that the operation may be 'promoted' which means that it is
> + // 'bitcasted' to another type which is handled.
> + if (TLI.getOperationAction(ISD::AND, VT) == TargetLowering::Expand ||
> + TLI.getOperationAction(ISD::XOR, VT) == TargetLowering::Expand ||
> + TLI.getOperationAction(ISD::OR, VT) == TargetLowering::Expand)
> + return DAG.UnrollVectorOp(Op.getNode());
>
> assert(VT.getSizeInBits() == Op.getOperand(1).getValueType().getSizeInBits()
> && "Invalid mask size");
> @@ -421,9 +423,9 @@
> DebugLoc DL = Op.getDebugLoc();
>
> // Make sure that the SINT_TO_FP and SRL instructions are available.
> - if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, VT) ||
> - !TLI.isOperationLegalOrCustom(ISD::SRL, VT))
> - return DAG.UnrollVectorOp(Op.getNode());
> + if (TLI.getOperationAction(ISD::SINT_TO_FP, VT) == TargetLowering::Expand ||
> + TLI.getOperationAction(ISD::SRL, VT) == TargetLowering::Expand)
> + return DAG.UnrollVectorOp(Op.getNode());
Have you considered to use a helper function here ?
-
Devang
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