[llvm-commits] [llvm] r142397 - in /llvm/trunk: include/llvm/Target/Target.td lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td
Jim Grosbach
grosbach at apple.com
Tue Oct 18 13:34:40 PDT 2011
Excellent! Very nice to get that cleaned up.
-Jim
On Oct 18, 2011, at 12:18 PM, Andrew Trick wrote:
> Author: atrick
> Date: Tue Oct 18 14:18:52 2011
> New Revision: 142397
>
> URL: http://llvm.org/viewvc/llvm-project?rev=142397&view=rev
> Log:
> Use ARM/t2PseudoInst class from ARM/Thumb2 special adds/subs patterns.
>
> Clean up the patterns, fix comments, and avoid confusing both tools
> and coders. Note that the special adds/subs SelectionDAG nodes no
> longer have the dummy cc_out operand.
>
> Modified:
> llvm/trunk/include/llvm/Target/Target.td
> llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
> llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
> llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
> llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
>
> Modified: llvm/trunk/include/llvm/Target/Target.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Target.td?rev=142397&r1=142396&r2=142397&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Target/Target.td (original)
> +++ llvm/trunk/include/llvm/Target/Target.td Tue Oct 18 14:18:52 2011
> @@ -356,6 +356,15 @@
> // associated with them. Once we've migrated all of them over to true
> // pseudo-instructions that are lowered to real instructions prior to
> // the printer/emitter, we can remove this attribute and just use isPseudo.
> + //
> + // The intended use is:
> + // isPseudo: Does not have encoding information and should be expanded,
> + // at the latest, during lowering to MCInst.
> + //
> + // isCodeGenOnly: Does have encoding information and can go through to the
> + // CodeEmitter unchanged, but duplicates a canonical instruction
> + // definition's encoding and should be ignored when constructing the
> + // assembler match tables.
> bit isCodeGenOnly = 0;
>
> // Is this instruction a pseudo instruction for use by the assembler parser.
>
> Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=142397&r1=142396&r2=142397&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Oct 18 14:18:52 2011
> @@ -1478,7 +1478,6 @@
> {ARM::SUBSrsr, ARM::SUBrsr},
>
> {ARM::RSBSri, ARM::RSBri},
> - {ARM::RSBSrr, ARM::RSBrr},
> {ARM::RSBSrsi, ARM::RSBrsi},
> {ARM::RSBSrsr, ARM::RSBrsr},
>
>
> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=142397&r1=142396&r2=142397&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Oct 18 14:18:52 2011
> @@ -6319,8 +6319,8 @@
>
> void ARMTargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
> SDNode *Node) const {
> - const MCInstrDesc &MCID = MI->getDesc();
> - if (!MCID.hasPostISelHook()) {
> + const MCInstrDesc *MCID = &MI->getDesc();
> + if (!MCID->hasPostISelHook()) {
> assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
> "Pseudo flag-setting opcodes must be marked with 'hasPostISelHook'");
> return;
> @@ -6331,20 +6331,28 @@
> // operand is still set to noreg. If needed, set the optional operand's
> // register to CPSR, and remove the redundant implicit def.
> //
> - // e.g. ADCS (...opt:%noreg, CPSR<imp-def>) -> ADC (... opt:CPSR<def>).
> + // e.g. ADCS (..., CPSR<imp-def>) -> ADC (... opt:CPSR<def>).
>
> // Rename pseudo opcodes.
> unsigned NewOpc = convertAddSubFlagsOpcode(MI->getOpcode());
> if (NewOpc) {
> const ARMBaseInstrInfo *TII =
> static_cast<const ARMBaseInstrInfo*>(getTargetMachine().getInstrInfo());
> - MI->setDesc(TII->get(NewOpc));
> + MCID = &TII->get(NewOpc);
> +
> + assert(MCID->getNumOperands() == MI->getDesc().getNumOperands() + 1 &&
> + "converted opcode should be the same except for cc_out");
> +
> + MI->setDesc(*MCID);
> +
> + // Add the optional cc_out operand
> + MI->addOperand(MachineOperand::CreateReg(0, /*isDef=*/true));
> }
> - unsigned ccOutIdx = MCID.getNumOperands() - 1;
> + unsigned ccOutIdx = MCID->getNumOperands() - 1;
>
> // Any ARM instruction that sets the 's' bit should specify an optional
> // "cc_out" operand in the last operand position.
> - if (!MCID.hasOptionalDef() || !MCID.OpInfo[ccOutIdx].isOptionalDef()) {
> + if (!MCID->hasOptionalDef() || !MCID->OpInfo[ccOutIdx].isOptionalDef()) {
> assert(!NewOpc && "Optional cc_out operand required");
> return;
> }
> @@ -6352,7 +6360,7 @@
> // since we already have an optional CPSR def.
> bool definesCPSR = false;
> bool deadCPSR = false;
> - for (unsigned i = MCID.getNumOperands(), e = MI->getNumOperands();
> + for (unsigned i = MCID->getNumOperands(), e = MI->getNumOperands();
> i != e; ++i) {
> const MachineOperand &MO = MI->getOperand(i);
> if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) {
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=142397&r1=142396&r2=142397&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Oct 18 14:18:52 2011
> @@ -1040,69 +1040,58 @@
>
> }
>
> -/// AsI1_rbin_s_is - Same as AsI1_rbin_s_is except it sets 's' bit by default.
> +/// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
> ///
> /// These opcodes will be converted to the real non-S opcodes by
> -/// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
> -let hasPostISelHook = 1, isCodeGenOnly = 1, isPseudo = 1, Defs = [CPSR] in {
> -multiclass AsI1_rbin_s_is<bits<4> opcod, string opc,
> - InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
> - PatFrag opnode, bit Commutable = 0> {
> - def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
> - iii, opc, "\t$Rd, $Rn, $imm",
> - [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]>;
> -
> - def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
> - iir, opc, "\t$Rd, $Rn, $Rm",
> - [/* pattern left blank */]>;
> -
> - def rsi : AsI1<opcod, (outs GPR:$Rd),
> - (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
> - iis, opc, "\t$Rd, $Rn, $shift",
> - [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift, GPR:$Rn))]>;
> -
> - def rsr : AsI1<opcod, (outs GPR:$Rd),
> - (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
> - iis, opc, "\t$Rd, $Rn, $shift",
> - [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift, GPR:$Rn))]> {
> - bits<4> Rd;
> - bits<4> Rn;
> - bits<12> shift;
> - let Inst{25} = 0;
> - let Inst{19-16} = Rn;
> - let Inst{15-12} = Rd;
> - let Inst{11-8} = shift{11-8};
> - let Inst{7} = 0;
> - let Inst{6-5} = shift{6-5};
> - let Inst{4} = 1;
> - let Inst{3-0} = shift{3-0};
> +/// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
> +let hasPostISelHook = 1, Defs = [CPSR] in {
> +multiclass AsI1_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
> + InstrItinClass iis, PatFrag opnode,
> + bit Commutable = 0> {
> + def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
> + 4, iii,
> + [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]>;
> +
> + def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
> + 4, iir,
> + [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]> {
> + let isCommutable = Commutable;
> }
> + def rsi : ARMPseudoInst<(outs GPR:$Rd),
> + (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
> + 4, iis,
> + [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
> + so_reg_imm:$shift))]>;
> +
> + def rsr : ARMPseudoInst<(outs GPR:$Rd),
> + (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
> + 4, iis,
> + [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
> + so_reg_reg:$shift))]>;
> }
> }
>
> -/// AsI1_bin_s_irs - Same as AsI1_bin_irs except it sets the 's' bit by default.
> -///
> -/// These opcodes will be converted to the real non-S opcodes by
> -/// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
> -let hasPostISelHook = 1, isCodeGenOnly = 1, isPseudo = 1, Defs = [CPSR] in {
> -multiclass AsI1_bin_s_irs<bits<4> opcod, string opc,
> - InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
> - PatFrag opnode, bit Commutable = 0> {
> - def ri : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
> - iii, opc, "\t$Rd, $Rn, $imm",
> - [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]>;
> - def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
> - iir, opc, "\t$Rd, $Rn, $Rm",
> - [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>;
> - def rsi : AsI1<opcod, (outs GPR:$Rd),
> - (ins GPR:$Rn, so_reg_imm:$shift), DPSoRegImmFrm,
> - iis, opc, "\t$Rd, $Rn, $shift",
> - [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_imm:$shift))]>;
> -
> - def rsr : AsI1<opcod, (outs GPR:$Rd),
> - (ins GPR:$Rn, so_reg_reg:$shift), DPSoRegRegFrm,
> - iis, opc, "\t$Rd, $Rn, $shift",
> - [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_reg_reg:$shift))]>;
> +/// AsI1_rbin_s_is - Same as AsI1_bin_s_irs, except selection DAG
> +/// operands are reversed.
> +let hasPostISelHook = 1, Defs = [CPSR] in {
> +multiclass AsI1_rbin_s_is<InstrItinClass iii, InstrItinClass iir,
> + InstrItinClass iis, PatFrag opnode,
> + bit Commutable = 0> {
> + def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
> + 4, iii,
> + [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]>;
> +
> + def rsi : ARMPseudoInst<(outs GPR:$Rd),
> + (ins GPR:$Rn, so_reg_imm:$shift, pred:$p),
> + 4, iis,
> + [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
> + GPR:$Rn))]>;
> +
> + def rsr : ARMPseudoInst<(outs GPR:$Rd),
> + (ins GPR:$Rn, so_reg_reg:$shift, pred:$p),
> + 4, iis,
> + [(set GPR:$Rd, CPSR, (opnode so_reg_reg:$shift,
> + GPR:$Rn))]>;
> }
> }
>
> @@ -2859,7 +2848,7 @@
> let Inst{15-12} = Rd;
> }
>
> -def : ARMInstAlias<"movs${p} $Rd, $Rm",
> +def : ARMInstAlias<"movs${p} $Rd, $Rm",
> (MOVr GPR:$Rd, GPR:$Rm, pred:$p, CPSR)>;
>
> // A version for the smaller set of tail call registers.
> @@ -3079,20 +3068,18 @@
>
> // ADD and SUB with 's' bit set.
> //
> -// Currently, t2ADDS/t2SUBS are pseudo opcodes that exist only in the
> -// selection DAG. They are "lowered" to real t2ADD/t2SUB opcodes by
> +// Currently, ADDS/SUBS are pseudo opcodes that exist only in the
> +// selection DAG. They are "lowered" to real ADD/SUB opcodes by
> // AdjustInstrPostInstrSelection where we determine whether or not to
> // set the "s" bit based on CPSR liveness.
> //
> -// FIXME: Eliminate t2ADDS/t2SUBS pseudo opcodes after adding tablegen
> +// FIXME: Eliminate ADDS/SUBS pseudo opcodes after adding tablegen
> // support for an optional CPSR definition that corresponds to the DAG
> // node's second value. We can then eliminate the implicit def of CPSR.
> -defm ADDS : AsI1_bin_s_irs<0b0100, "add",
> - IIC_iALUi, IIC_iALUr, IIC_iALUsr,
> - BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
> -defm SUBS : AsI1_bin_s_irs<0b0010, "sub",
> - IIC_iALUi, IIC_iALUr, IIC_iALUsr,
> - BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
> +defm ADDS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
> + BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
> +defm SUBS : AsI1_bin_s_irs<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
> + BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
>
> defm ADC : AI1_adde_sube_irs<0b0101, "adc",
> BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>,
> @@ -3107,9 +3094,8 @@
>
> // FIXME: Eliminate them if we can write def : Pat patterns which defines
> // CPSR and the implicit def of CPSR is not needed.
> -defm RSBS : AsI1_rbin_s_is<0b0011, "rsb",
> - IIC_iALUi, IIC_iALUr, IIC_iALUsr,
> - BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
> +defm RSBS : AsI1_rbin_s_is<IIC_iALUi, IIC_iALUr, IIC_iALUsr,
> + BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
>
> defm RSC : AI1_rsc_irs<0b0111, "rsc",
> BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>,
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=142397&r1=142396&r2=142397&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Oct 18 14:18:52 2011
> @@ -608,25 +608,48 @@
> ///
> /// These opcodes will be converted to the real non-S opcodes by
> /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
> -let hasPostISelHook = 1, isCodeGenOnly = 1, isPseudo = 1, Defs = [CPSR] in {
> -multiclass T2I_bin_s_irs<bits<4> opcod, string opc,
> - InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
> - PatFrag opnode, bit Commutable = 0> {
> +let hasPostISelHook = 1, Defs = [CPSR] in {
> +multiclass T2I_bin_s_irs<InstrItinClass iii, InstrItinClass iir,
> + InstrItinClass iis, PatFrag opnode,
> + bit Commutable = 0> {
> // shifted imm
> - def ri : T2sTwoRegImm<
> - (outs rGPR:$Rd), (ins GPRnopc:$Rn, t2_so_imm:$imm), iii,
> - opc, ".w\t$Rd, $Rn, $imm",
> - [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]>;
> + def ri : t2PseudoInst<(outs rGPR:$Rd),
> + (ins GPRnopc:$Rn, t2_so_imm:$imm, pred:$p),
> + 4, iii,
> + [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
> + t2_so_imm:$imm))]>;
> // register
> - def rr : T2sThreeReg<
> - (outs rGPR:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm), iir,
> - opc, ".w\t$Rd, $Rn, $Rm",
> - [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn, rGPR:$Rm))]>;
> + def rr : t2PseudoInst<(outs rGPR:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm, pred:$p),
> + 4, iir,
> + [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
> + rGPR:$Rm))]> {
> + let isCommutable = Commutable;
> + }
> // shifted register
> - def rs : T2sTwoRegShiftedReg<
> - (outs rGPR:$Rd), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), iis,
> - opc, ".w\t$Rd, $Rn, $ShiftedRm",
> - [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]>;
> + def rs : t2PseudoInst<(outs rGPR:$Rd),
> + (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm, pred:$p),
> + 4, iis,
> + [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
> + t2_so_reg:$ShiftedRm))]>;
> +}
> +}
> +
> +/// T2I_rbin_s_is - Same as T2I_bin_s_irs, except selection DAG
> +/// operands are reversed.
> +let hasPostISelHook = 1, Defs = [CPSR] in {
> +multiclass T2I_rbin_s_is<PatFrag opnode> {
> + // shifted imm
> + def ri : t2PseudoInst<(outs rGPR:$Rd),
> + (ins GPRnopc:$Rn, t2_so_imm:$imm, pred:$p),
> + 4, IIC_iALUi,
> + [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm,
> + GPRnopc:$Rn))]>;
> + // shifted register
> + def rs : t2PseudoInst<(outs rGPR:$Rd),
> + (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm, pred:$p),
> + 4, IIC_iALUsi,
> + [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm,
> + GPRnopc:$Rn))]>;
> }
> }
>
> @@ -735,26 +758,6 @@
> }
> }
>
> -/// T2I_rbin_s_is - Same as T2I_rbin_irs except sets 's' bit and the register
> -/// version is not needed since this is only for codegen.
> -///
> -/// These opcodes will be converted to the real non-S opcodes by
> -/// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
> -let hasPostISelHook = 1, isCodeGenOnly = 1, isPseudo = 1, Defs = [CPSR] in {
> -multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> {
> - // shifted imm
> - def ri : T2sTwoRegImm<
> - (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi,
> - opc, ".w\t$Rd, $Rn, $imm",
> - [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm, rGPR:$Rn))]>;
> - // shifted register
> - def rs : T2sTwoRegShiftedReg<
> - (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm),
> - IIC_iALUsi, opc, "\t$Rd, $Rn, $ShiftedRm",
> - [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]>;
> -}
> -}
> -
> /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift /
> // rotate operation that produces a value.
> multiclass T2I_sh_ir<bits<2> opcod, string opc, Operand ty, PatFrag opnode,
> @@ -1845,11 +1848,9 @@
> // FIXME: Eliminate t2ADDS/t2SUBS pseudo opcodes after adding tablegen
> // support for an optional CPSR definition that corresponds to the DAG
> // node's second value. We can then eliminate the implicit def of CPSR.
> -defm t2ADDS : T2I_bin_s_irs <0b1000, "add",
> - IIC_iALUi, IIC_iALUr, IIC_iALUsi,
> +defm t2ADDS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi,
> BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>;
> -defm t2SUBS : T2I_bin_s_irs <0b1101, "sub",
> - IIC_iALUi, IIC_iALUr, IIC_iALUsi,
> +defm t2SUBS : T2I_bin_s_irs <IIC_iALUi, IIC_iALUr, IIC_iALUsi,
> BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
>
> let hasPostISelHook = 1 in {
> @@ -1865,8 +1866,7 @@
>
> // FIXME: Eliminate them if we can write def : Pat patterns which defines
> // CPSR and the implicit def of CPSR is not needed.
> -defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb",
> - BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
> +defm t2RSBS : T2I_rbin_s_is <BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>;
>
> // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
> // The assume-no-carry-in form uses the negation of the input since add/sub
>
>
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