[llvm-commits] [llvm] r142413 - in /llvm/trunk: lib/Target/ARM/ARMInstrNEON.td test/MC/ARM/neont2-mul-accum-encoding.s
Jim Grosbach
grosbach at apple.com
Tue Oct 18 13:14:56 PDT 2011
Author: grosbach
Date: Tue Oct 18 15:14:56 2011
New Revision: 142413
URL: http://llvm.org/viewvc/llvm-project?rev=142413&view=rev
Log:
ARM vmla/vmls assembly parsing for the lane index operand.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
llvm/trunk/test/MC/ARM/neont2-mul-accum-encoding.s
Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=142413&r1=142412&r2=142413&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Tue Oct 18 15:14:56 2011
@@ -2204,9 +2204,9 @@
InstrItinClass itin, string OpcodeStr, string Dt,
ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
: N3VLane32<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
- (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, nohash_imm:$lane),
+ (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
NVMulSLFrm, itin,
- OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
+ OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
[(set QPR:$Vd,
(OpNode (TyQ QPR:$src1),
(TyQ (MulOp (TyD DPR:$Vn),
@@ -2216,9 +2216,9 @@
InstrItinClass itin, string OpcodeStr, string Dt,
ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
: N3VLane16<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
- (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, nohash_imm:$lane),
+ (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
NVMulSLFrm, itin,
- OpcodeStr, Dt, "$Vd, $Vn, $Vm[$lane]", "$src1 = $Vd",
+ OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
[(set QPR:$Vd,
(OpNode (TyQ QPR:$src1),
(TyQ (MulOp (TyD DPR:$Vn),
Modified: llvm/trunk/test/MC/ARM/neont2-mul-accum-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-mul-accum-encoding.s?rev=142413&r1=142412&r2=142413&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neont2-mul-accum-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neont2-mul-accum-encoding.s Tue Oct 18 15:14:56 2011
@@ -29,7 +29,7 @@
vmlal.u8 q8, d19, d18
vmlal.u16 q8, d19, d18
vmlal.u32 q8, d19, d18
-@ vmlal.s32 q0, d5, d10[0]
+ vmlal.s32 q0, d5, d10[0]
@ CHECK: vmlal.s8 q8, d19, d18 @ encoding: [0xc3,0xef,0xa2,0x08]
@ CHECK: vmlal.s16 q8, d19, d18 @ encoding: [0xd3,0xef,0xa2,0x08]
@@ -37,7 +37,7 @@
@ CHECK: vmlal.u8 q8, d19, d18 @ encoding: [0xc3,0xff,0xa2,0x08]
@ CHECK: vmlal.u16 q8, d19, d18 @ encoding: [0xd3,0xff,0xa2,0x08]
@ CHECK: vmlal.u32 q8, d19, d18 @ encoding: [0xe3,0xff,0xa2,0x08]
-@ FIXME: vmlal.s32 q0, d5, d10[0] @ encoding: [0xa5,0xef,0x4a,0x02]
+@ CHECK: vmlal.s32 q0, d5, d10[0] @ encoding: [0xa5,0xef,0x4a,0x02]
vqdmlal.s16 q8, d19, d18
@@ -82,7 +82,7 @@
vmlsl.u8 q8, d19, d18
vmlsl.u16 q8, d19, d18
vmlsl.u32 q8, d19, d18
-@ vmlsl.u16 q11, d25, d1[3]
+ vmlsl.u16 q11, d25, d1[3]
@ CHECK: vmlsl.s8 q8, d19, d18 @ encoding: [0xc3,0xef,0xa2,0x0a]
@ CHECK: vmlsl.s16 q8, d19, d18 @ encoding: [0xd3,0xef,0xa2,0x0a]
@@ -90,7 +90,7 @@
@ CHECK: vmlsl.u8 q8, d19, d18 @ encoding: [0xc3,0xff,0xa2,0x0a]
@ CHECK: vmlsl.u16 q8, d19, d18 @ encoding: [0xd3,0xff,0xa2,0x0a]
@ CHECK: vmlsl.u32 q8, d19, d18 @ encoding: [0xe3,0xff,0xa2,0x0a]
-@ FIXME: vmlsl.u16 q11, d25, d1[3] @ encoding: [0xd9,0xff,0xe9,0x66]
+@ CHECK: vmlsl.u16 q11, d25, d1[3] @ encoding: [0xd9,0xff,0xe9,0x66]
vqdmlsl.s16 q8, d19, d18
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