[llvm-commits] [llvm] r142377 - in /llvm/trunk/test/MC/ARM: neont2-mul-accum-encoding.s neont2-mul-encoding.s

[Owen Anderson]

Author: resistor
Date: Tue Oct 18 12:50:22 2011
New Revision: 142377

URL: http://llvm.org/viewvc/llvm-project?rev=142377&view=rev
Log:
Add several FIXME cases for ARM encodings.

Modified:
    llvm/trunk/test/MC/ARM/neont2-mul-accum-encoding.s
    llvm/trunk/test/MC/ARM/neont2-mul-encoding.s

Modified: llvm/trunk/test/MC/ARM/neont2-mul-accum-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-mul-accum-encoding.s?rev=142377&r1=142376&r2=142377&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neont2-mul-accum-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neont2-mul-accum-encoding.s Tue Oct 18 12:50:22 2011
@@ -90,3 +90,8 @@
 
 @ CHECK: vqdmlsl.s16	q8, d19, d18    @ encoding: [0xd3,0xef,0xa2,0x0b]
 @ CHECK: vqdmlsl.s32	q8, d19, d18    @ encoding: [0xe3,0xef,0xa2,0x0b]
+
+@  vmla.i32	q12, q8, d3[0]
+@ FIXME: vmla.i32	q12, q8, d3[0]    @ encoding: [0xe0,0xff,0xc3,0x80]
+@  vmlal.s32	q0, d5, d10[0]
+@ FIXME: vmlal.s32	q0, d5, d10[0]    @ encoding: [0xa5,0xef,0x4a,0x02]

Modified: llvm/trunk/test/MC/ARM/neont2-mul-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neont2-mul-encoding.s?rev=142377&r1=142376&r2=142377&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neont2-mul-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neont2-mul-encoding.s Tue Oct 18 12:50:22 2011
@@ -56,3 +56,12 @@
 	vqdmull.s16	q8, d16, d17
 @ CHECK: vqdmull.s32	q8, d16, d17    @ encoding: [0xe0,0xef,0xa1,0x0d]
 	vqdmull.s32	q8, d16, d17
+
+@ FIXME: vmla.i32	q12, q8, d3[0]    @ encoding: [0xe0,0xff,0xc3,0x80]
+@  vmla.i32	q12, q8, d3[0]
+@ FIXME: vqdmulh.s16	d11, d2, d3[0]    @ encoding: [0x92,0xef,0x43,0xbc]
+@  vqdmulh.s16	d11, d2, d3[0]
+@ FIXME: vmul.i16	d18, d8, d0[3]    @ encoding: [0xd8,0xef,0x68,0x28]
+@  vmul.i16	d18, d8, d0[3]
+
+