[llvm-commits] [llvm] r142152 - in /llvm/trunk: lib/CodeGen/SelectionDAG/ test/CodeGen/ARM/ test/CodeGen/CellSPU/ test/CodeGen/X86/

[Rotem, Nadav]

Kalle, 

You can disable this feature by setting the llc flag '-promote-elements=false'. I noticed that the SPU backend does not implement the vector SHL operation properly which makes SIGN_EXTEND_INREG very inefficient. Any chance that you fix this ?
 
Thanks,
Nadav

-----Original Message-----
From: Kalle Raiskila [mailto:kalle.raiskila at nokia.com] 
Sent: Monday, October 17, 2011 12:11
To: Rotem, Nadav
Cc: llvm-commits at cs.uiuc.edu
Subject: Re: [llvm-commits] [llvm] r142152 - in /llvm/trunk: lib/CodeGen/SelectionDAG/ test/CodeGen/ARM/ test/CodeGen/CellSPU/ test/CodeGen/X86/

On 16/10/11 23:31, ext Nadav Rotem wrote:
> Author: nadav
> Date: Sun Oct 16 15:31:33 2011
> New Revision: 142152
>
> URL: http://llvm.org/viewvc/llvm-project?rev=142152&view=rev
> Log:
> Enable element promotion type legalization by deafault.
> Changed tests which assumed that vectors are legalized by widening them.

How does one disable this per instruction/vectortype/backend?

Because e.g. the runtime of this:

>   define %vec @test_add(%vec %param)
>   {
> -;CHECK: a {{\$.}}, $3, $3
> +;CHECK: shufb
> +;CHECK: addx
>     %1 = add %vec %param, %param
>   ;CHECK: bi $lr
>     ret %vec %1
> @@ -17,21 +18,14 @@

increased from 2 to 12 cycles when %vec is <2 x i32>

thanks,
kalle
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