[llvm-commits] [llvm] r142152 - in /llvm/trunk: lib/CodeGen/SelectionDAG/ test/CodeGen/ARM/ test/CodeGen/CellSPU/ test/CodeGen/X86/

[Rotem, Nadav]

Hi Owen,

Thanks for looking at this.  I restored the CHECKs and added some documentation.  Let me explain the recent changes to the type-legalizer and how it affects the ARM backend.

Previously the type-legalizer changed <2 x i16> into <4 x i16>.  Currently, the type legalizer attempts to widen each element first.  So <2 x i16> is promoted to <2 x i32>.  Generally, this is a good change for ARM because it maps better to the sparse vector architectures (not to mention that it enables the use of NEON masks using vectors of i1's). Usually, the common types are better supported on vector architectures.

Let me point out another example. Consider the following operation MUL v4i8;   On x86, the llvm codegen would promote it to v16i8, only to discover that there is no v16i8 multiplication operation, and scalarize the operation to 16 scalar multiplications. So, as this example shows, promoting elements is beneficial in many cases.

The new type-legalization generates new code sequences. For example: trunc store and anyext loads.  I implemented fast load/store sequences  for x86.  Other targets also need to optimize the new sequences.  I opened a bug report on this PR11158.

Thanks,
Nadav


From: Owen Anderson [mailto:resistor at mac.com]
Sent: Monday, October 17, 2011 19:42
To: Rotem, Nadav
Cc: llvm-commits at cs.uiuc.edu
Subject: Re: [llvm-commits] [llvm] r142152 - in /llvm/trunk: lib/CodeGen/SelectionDAG/ test/CodeGen/ARM/ test/CodeGen/CellSPU/ test/CodeGen/X86/


On Oct 17, 2011, at 10:29 AM, Owen Anderson wrote:


Nadav,


On Oct 16, 2011, at 1:31 PM, Nadav Rotem wrote:


Author: nadav
Date: Sun Oct 16 15:31:33 2011
New Revision: 142152

...


Modified: llvm/trunk/test/CodeGen/ARM/vrev.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vrev.ll?rev=142152&r1=142151&r2=142152&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vrev.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/vrev.ll Sun Oct 16 15:31:33 2011
@@ -150,9 +150,6 @@

; vrev <4 x i16> should use VREV32 and not VREV64
define void @test_vrev64(<4 x i16>* nocapture %source, <2 x i16>* nocapture %dst) nounwind ssp {
-; CHECK: test_vrev64:
-; CHECK: vext.16
-; CHECK: vrev32.16
entry:
 %0 = bitcast <4 x i16>* %source to <8 x i16>*
 %tmp2 = load <8 x i16>* %0, align 4

You've removed all the CHECK lines from this test, essentially disabling it.  Please make sure it still works and add back correct CHECK lines.

To follow up on my own post, it does not still work.  The new generated code is MUCH worse than what is being checked for, involve extra stores rather than a shuffle instruction.  Please fix this or re-disable this patch until it can be fixed.

--Owen
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