[llvm-commits] [llvm] r142214 - in /llvm/trunk/lib/Target/Mips: Mips64InstrInfo.td MipsInstrInfo.td
Akira Hatanaka
ahatanaka at mips.com
Mon Oct 17 11:24:15 PDT 2011
Author: ahatanak
Date: Mon Oct 17 13:24:15 2011
New Revision: 142214
URL: http://llvm.org/viewvc/llvm-project?rev=142214&view=rev
Log:
Redefine mfhi/lo and mthi/lo instructions.
Modified:
llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=142214&r1=142213&r2=142214&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Mon Oct 17 13:24:15 2011
@@ -57,19 +57,6 @@
class Div64<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
Div<op, func, instr_asm, itin, CPU64Regs, [HI64, LO64]>;
-// Move from Hi/Lo
-let shamt = 0 in {
-let rs = 0, rt = 0 in
-class MoveFromLOHI64<bits<6> func, string instr_asm>:
- FR<0x00, func, (outs CPU64Regs:$dst), (ins),
- !strconcat(instr_asm, "\t$dst"), [], IIHiLo>;
-
-let rt = 0, rd = 0 in
-class MoveToLOHI64<bits<6> func, string instr_asm>:
- FR<0x00, func, (outs), (ins CPU64Regs:$src),
- !strconcat(instr_asm, "\t$src"), [], IIHiLo>;
-}
-
// Count Leading Ones/Zeros in Word
class CountLeading64<bits<6> func, string instr_asm, list<dag> pattern>:
FR<0x1c, func, (outs CPU64Regs:$dst), (ins CPU64Regs:$src),
@@ -157,15 +144,10 @@
def DSDIV : Div64<MipsDivRem, 0x1e, "ddiv", IIIdiv>;
def DUDIV : Div64<MipsDivRemU, 0x1f, "ddivu", IIIdiv>;
-let Defs = [HI64] in
- def MTHI64 : MoveToLOHI64<0x11, "mthi">;
-let Defs = [LO64] in
- def MTLO64 : MoveToLOHI64<0x13, "mtlo">;
-
-let Uses = [HI64] in
- def MFHI64 : MoveFromLOHI64<0x10, "mfhi">;
-let Uses = [LO64] in
- def MFLO64 : MoveFromLOHI64<0x12, "mflo">;
+def MTHI64 : MoveToLOHI<0x11, "mthi", CPU64Regs, [HI64]>;
+def MTLO64 : MoveToLOHI<0x13, "mtlo", CPU64Regs, [LO64]>;
+def MFHI64 : MoveFromLOHI<0x10, "mfhi", CPU64Regs, [HI64]>;
+def MFLO64 : MoveFromLOHI<0x12, "mflo", CPU64Regs, [LO64]>;
/// Count Leading
def DCLZ : CountLeading64<0x24, "dclz",
Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=142214&r1=142213&r2=142214&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Mon Oct 17 13:24:15 2011
@@ -488,20 +488,24 @@
Div<op, func, instr_asm, itin, CPURegs, [HI, LO]>;
// Move from Hi/Lo
-class MoveFromLOHI<bits<6> func, string instr_asm>:
- FR<0x00, func, (outs CPURegs:$rd), (ins),
+class MoveFromLOHI<bits<6> func, string instr_asm, RegisterClass RC,
+ list<Register> UseRegs>:
+ FR<0x00, func, (outs RC:$rd), (ins),
!strconcat(instr_asm, "\t$rd"), [], IIHiLo> {
let rs = 0;
let rt = 0;
let shamt = 0;
+ let Uses = UseRegs;
}
-class MoveToLOHI<bits<6> func, string instr_asm>:
- FR<0x00, func, (outs), (ins CPURegs:$rs),
+class MoveToLOHI<bits<6> func, string instr_asm, RegisterClass RC,
+ list<Register> DefRegs>:
+ FR<0x00, func, (outs), (ins RC:$rs),
!strconcat(instr_asm, "\t$rs"), [], IIHiLo> {
let rt = 0;
let rd = 0;
let shamt = 0;
+ let Defs = DefRegs;
}
class EffectiveAddress<string instr_asm> :
@@ -739,15 +743,10 @@
def SDIV : Div32<MipsDivRem, 0x1a, "div", IIIdiv>;
def UDIV : Div32<MipsDivRemU, 0x1b, "divu", IIIdiv>;
-let Defs = [HI] in
- def MTHI : MoveToLOHI<0x11, "mthi">;
-let Defs = [LO] in
- def MTLO : MoveToLOHI<0x13, "mtlo">;
-
-let Uses = [HI] in
- def MFHI : MoveFromLOHI<0x10, "mfhi">;
-let Uses = [LO] in
- def MFLO : MoveFromLOHI<0x12, "mflo">;
+def MTHI : MoveToLOHI<0x11, "mthi", CPURegs, [HI]>;
+def MTLO : MoveToLOHI<0x13, "mtlo", CPURegs, [LO]>;
+def MFHI : MoveFromLOHI<0x10, "mfhi", CPURegs, [HI]>;
+def MFLO : MoveFromLOHI<0x12, "mflo", CPURegs, [LO]>;
/// Sign Ext In Register Instructions.
def SEB : SignExtInReg<0x10, "seb", i8>;
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