[llvm-commits] [llvm] r142152 - in /llvm/trunk: lib/CodeGen/SelectionDAG/ test/CodeGen/ARM/ test/CodeGen/CellSPU/ test/CodeGen/X86/
Kalle Raiskila
kalle.raiskila at nokia.com
Mon Oct 17 03:11:17 PDT 2011
On 16/10/11 23:31, ext Nadav Rotem wrote:
> Author: nadav
> Date: Sun Oct 16 15:31:33 2011
> New Revision: 142152
>
> URL: http://llvm.org/viewvc/llvm-project?rev=142152&view=rev
> Log:
> Enable element promotion type legalization by deafault.
> Changed tests which assumed that vectors are legalized by widening them.
How does one disable this per instruction/vectortype/backend?
Because e.g. the runtime of this:
> define %vec @test_add(%vec %param)
> {
> -;CHECK: a {{\$.}}, $3, $3
> +;CHECK: shufb
> +;CHECK: addx
> %1 = add %vec %param, %param
> ;CHECK: bi $lr
> ret %vec %1
> @@ -17,21 +18,14 @@
increased from 2 to 12 cycles when %vec is <2 x i32>
thanks,
kalle
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