[llvm-commits] [llvm] r142130 - in /llvm/trunk: lib/Target/CellSPU/SPUISelLowering.cpp test/CodeGen/CellSPU/shift_ops.ll
Nadav Rotem
nadav.rotem at intel.com
Sun Oct 16 03:02:06 PDT 2011
Author: nadav
Date: Sun Oct 16 05:02:06 2011
New Revision: 142130
URL: http://llvm.org/viewvc/llvm-project?rev=142130&view=rev
Log:
Fix a bug in LowerV2I64Splat, which generated a BUILD_VECTOR for which there was
no pattern.
Modified:
llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
llvm/trunk/test/CodeGen/CellSPU/shift_ops.ll
Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=142130&r1=142129&r2=142130&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Sun Oct 16 05:02:06 2011
@@ -1752,9 +1752,11 @@
// Both upper and lower are special, lower to a constant pool load:
if (lower_special && upper_special) {
- SDValue SplatValCN = DAG.getConstant(SplatVal, MVT::i64);
- return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64,
- SplatValCN, SplatValCN);
+ SDValue UpperVal = DAG.getConstant(upper, MVT::i32);
+ SDValue LowerVal = DAG.getConstant(lower, MVT::i32);
+ SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
+ UpperVal, LowerVal, UpperVal, LowerVal);
+ return DAG.getNode(ISD::BITCAST, dl, OpVT, BV);
}
SDValue LO32;
Modified: llvm/trunk/test/CodeGen/CellSPU/shift_ops.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CellSPU/shift_ops.ll?rev=142130&r1=142129&r2=142130&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/CellSPU/shift_ops.ll (original)
+++ llvm/trunk/test/CodeGen/CellSPU/shift_ops.ll Sun Oct 16 05:02:06 2011
@@ -342,3 +342,7 @@
%rv = ashr <8 x i16> %val, %sh
ret <8 x i16> %rv
}
+
+define <2 x i64> @special_const() {
+ ret <2 x i64> <i64 4294967295, i64 4294967295>
+}
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