[llvm-commits] [llvm] r141854 - in /llvm/trunk: lib/Target/X86/X86.td lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrInfo.td lib/Target/X86/X86Subtarget.h test/CodeGen/X86/bmi.ll test/MC/Disassembler/X86/simple-tests.txt test/MC/Disass
Craig Topper
craig.topper at gmail.com
Thu Oct 13 10:31:50 PDT 2011
Yeah I intend to update the AutoDetectSubtarget. I didn't do it yet because
it requires capturing the max leaf supported from leaf 0 so that we know if
leaf 7 is legal. Then we also need to pass 0 in ecx into cpuid to get the
right subleaf of leaf 7. That mucks with the cpuid routine that is branched
for different compilers so I need to be careful there.
On Thu, Oct 13, 2011 at 9:45 AM, Joe Abbey <jabbey at arxan.com> wrote:
> I see. Are you going to updating AutoDetectSubtarget features to check bit
> 8 of the Structured Extended Feature Leaf? Looks like there's more
> features.
>
> Bits 00: FSGS BASE
> Bits 02-01: Reserved.
> Bits 03: BMI1
> Bits 04: Reserved.
> Bits 05: AVX2
> Bits 07-06: Reserved.
> Bits 08: BMI2
>
Bits 09: ERMS
>
Bits 10: INVPCID
> Bits 31-11: Reserved.
>
> And add an initializer to the list for the constructor?
>
> Joe Abbey
> Software Architect
> Arxan Technologies, Inc.
> 1305 Cumberland Ave, Ste 215
> West Lafayette, IN 47906
> W: 765-889-4756 x2
> C: 765-464-9893
> jabbey at arxan.com
> www.arxan.com
>
>
> On Oct 13, 2011, at 12:18 PM, Craig Topper wrote:
>
> The test failed because the X86Subtarget constructor didn't initialize
> HasBMI to false. So the feature check in X86ISelLowering ends up reading
> from uninitialized memory and sometimes thinks its enabled. This causes
> ISelLowering to not run the custom lowering code, but the pattern matching
> code for instruction selection gets the feature enable a different way that
> correctly knows that BMI is disabled. So it was unable to find an
> instruction to use. I have a fix that I'll probably submit tonight.
>
> On Thu, Oct 13, 2011 at 9:04 AM, Joe Abbey <jabbey at arxan.com> wrote:
>
>> This patch enhances r141855 and fixes the failing test by adding the new
>> -mattr=+bmi target attribute.
>>
>> Craig, is that correct?
>>
>>
>>
>> Joe Abbey
>> Software Architect
>> Arxan Technologies, Inc.
>> 1305 Cumberland Ave, Ste 215
>> West Lafayette, IN 47906
>> W: 765-889-4756 x2
>> C: 765-464-9893
>> jabbey at arxan.com
>> www.arxan.com
>>
>>
>> On Oct 13, 2011, at 3:27 AM, Bill Wendling wrote:
>>
>> > Hi Craig,
>> >
>> > This is causing a failure on one of the public buildbots:
>> >
>> > http://lab.llvm.org:8011/builders/llvm-x86_64-linux/builds/101
>> >
>> > Could you take a look please?
>> >
>> > -bw
>> >
>> > On Oct 13, 2011, at 12:09 AM, Craig Topper wrote:
>> >
>> >> Author: ctopper
>> >> Date: Thu Oct 13 02:09:14 2011
>> >> New Revision: 141854
>> >>
>> >> URL: http://llvm.org/viewvc/llvm-project?rev=141854&view=rev
>> >> Log:
>> >> Add X86 TZCNT instruction and patterns to select it. Also added
>> core-avx2 processor which is gcc's name for Haswell.
>> >>
>> >> Added:
>> >> llvm/trunk/test/CodeGen/X86/bmi.ll
>> >> Modified:
>> >> llvm/trunk/lib/Target/X86/X86.td
>> >> llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>> >> llvm/trunk/lib/Target/X86/X86InstrInfo.td
>> >> llvm/trunk/lib/Target/X86/X86Subtarget.h
>> >> llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt
>> >> llvm/trunk/test/MC/Disassembler/X86/x86-32.txt
>> >>
>> >> Modified: llvm/trunk/lib/Target/X86/X86.td
>> >> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=141854&r1=141853&r2=141854&view=diff
>> >>
>> ==============================================================================
>> >> --- llvm/trunk/lib/Target/X86/X86.td (original)
>> >> +++ llvm/trunk/lib/Target/X86/X86.td Thu Oct 13 02:09:14 2011
>> >> @@ -104,6 +104,8 @@
>> >> "Support 16-bit floating point conversion
>> instructions">;
>> >> def FeatureLZCNT : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
>> >> "Support LZCNT instruction">;
>> >> +def FeatureBMI : SubtargetFeature<"bmi", "HasBMI", "true",
>> >> + "Support BMI instructions">;
>> >>
>> >>
>> //===----------------------------------------------------------------------===//
>> >> // X86 processors supported.
>> >> @@ -157,6 +159,11 @@
>> >> def : Proc<"core-avx-i", [FeatureSSE42, FeatureCMPXCHG16B,
>> >> FeatureAES, FeatureCLMUL,
>> >> FeatureRDRAND, FeatureF16C]>;
>> >> +// Haswell
>> >> +def : Proc<"core-avx2", [FeatureSSE42, FeatureCMPXCHG16B,
>> FeatureAES,
>> >> + FeatureCLMUL, FeatureRDRAND,
>> FeatureF16C,
>> >> + FeatureFMA3, FeatureMOVBE,
>> FeatureLZCNT,
>> >> + FeatureBMI]>;
>> >>
>> >> def : Proc<"k6", [FeatureMMX]>;
>> >> def : Proc<"k6-2", [Feature3DNow]>;
>> >>
>> >> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>> >> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=141854&r1=141853&r2=141854&view=diff
>> >>
>> ==============================================================================
>> >> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
>> >> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Oct 13 02:09:14
>> 2011
>> >> @@ -379,11 +379,15 @@
>> >> setOperationAction(ISD::FREM , MVT::f80 , Expand);
>> >> setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom);
>> >>
>> >> - setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
>> >> - setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
>> >> - setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
>> >> - if (Subtarget->is64Bit())
>> >> - setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
>> >> + if (Subtarget->hasBMI()) {
>> >> + setOperationAction(ISD::CTTZ , MVT::i8 , Promote);
>> >> + } else {
>> >> + setOperationAction(ISD::CTTZ , MVT::i8 , Custom);
>> >> + setOperationAction(ISD::CTTZ , MVT::i16 , Custom);
>> >> + setOperationAction(ISD::CTTZ , MVT::i32 , Custom);
>> >> + if (Subtarget->is64Bit())
>> >> + setOperationAction(ISD::CTTZ , MVT::i64 , Custom);
>> >> + }
>> >>
>> >> if (Subtarget->hasLZCNT()) {
>> >> setOperationAction(ISD::CTLZ , MVT::i8 , Promote);
>> >>
>> >> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
>> >> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=141854&r1=141853&r2=141854&view=diff
>> >>
>> ==============================================================================
>> >> --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
>> >> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Thu Oct 13 02:09:14 2011
>> >> @@ -478,6 +478,7 @@
>> >> def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">;
>> >> def HasF16C : Predicate<"Subtarget->hasF16C()">;
>> >> def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">;
>> >> +def HasBMI : Predicate<"Subtarget->hasBMI()">;
>> >> def FPStackf32 : Predicate<"!Subtarget->hasXMM()">;
>> >> def FPStackf64 : Predicate<"!Subtarget->hasXMMInt()">;
>> >> def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
>> >> @@ -1373,6 +1374,37 @@
>> >> }
>> >>
>> >>
>> //===----------------------------------------------------------------------===//
>> >> +// BMI Instructions
>> >> +//
>> >> +let Predicates = [HasBMI], Defs = [EFLAGS] in {
>> >> + def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins
>> GR16:$src),
>> >> + "tzcnt{w}\t{$src, $dst|$dst, $src}",
>> >> + [(set GR16:$dst, (cttz GR16:$src)), (implicit
>> EFLAGS)]>, XS,
>> >> + OpSize;
>> >> + def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins
>> i16mem:$src),
>> >> + "tzcnt{w}\t{$src, $dst|$dst, $src}",
>> >> + [(set GR16:$dst, (cttz (loadi16 addr:$src))),
>> >> + (implicit EFLAGS)]>, XS, OpSize;
>> >> +
>> >> + def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins
>> GR32:$src),
>> >> + "tzcnt{l}\t{$src, $dst|$dst, $src}",
>> >> + [(set GR32:$dst, (cttz GR32:$src)), (implicit
>> EFLAGS)]>, XS;
>> >> + def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins
>> i32mem:$src),
>> >> + "tzcnt{l}\t{$src, $dst|$dst, $src}",
>> >> + [(set GR32:$dst, (cttz (loadi32 addr:$src))),
>> >> + (implicit EFLAGS)]>, XS;
>> >> +
>> >> + def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins
>> GR64:$src),
>> >> + "tzcnt{q}\t{$src, $dst|$dst, $src}",
>> >> + [(set GR64:$dst, (cttz GR64:$src)), (implicit
>> EFLAGS)]>,
>> >> + XS;
>> >> + def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins
>> i64mem:$src),
>> >> + "tzcnt{q}\t{$src, $dst|$dst, $src}",
>> >> + [(set GR64:$dst, (cttz (loadi64 addr:$src))),
>> >> + (implicit EFLAGS)]>, XS;
>> >> +}
>> >> +
>> >>
>> +//===----------------------------------------------------------------------===//
>> >> // Subsystems.
>> >>
>> //===----------------------------------------------------------------------===//
>> >>
>> >>
>> >> Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h
>> >> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=141854&r1=141853&r2=141854&view=diff
>> >>
>> ==============================================================================
>> >> --- llvm/trunk/lib/Target/X86/X86Subtarget.h (original)
>> >> +++ llvm/trunk/lib/Target/X86/X86Subtarget.h Thu Oct 13 02:09:14 2011
>> >> @@ -102,6 +102,9 @@
>> >> /// HasLZCNT - Processor has LZCNT instruction.
>> >> bool HasLZCNT;
>> >>
>> >> + /// HasBMI - Processor has BMI1 instructions.
>> >> + bool HasBMI;
>> >> +
>> >> /// IsBTMemSlow - True if BT (bit test) of memory instructions are
>> slow.
>> >> bool IsBTMemSlow;
>> >>
>> >> @@ -188,6 +191,7 @@
>> >> bool hasRDRAND() const { return HasRDRAND; }
>> >> bool hasF16C() const { return HasF16C; }
>> >> bool hasLZCNT() const { return HasLZCNT; }
>> >> + bool hasBMI() const { return HasBMI; }
>> >> bool isBTMemSlow() const { return IsBTMemSlow; }
>> >> bool isUnalignedMemAccessFast() const { return IsUAMemFast; }
>> >> bool hasVectorUAMem() const { return HasVectorUAMem; }
>> >>
>> >> Added: llvm/trunk/test/CodeGen/X86/bmi.ll
>> >> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bmi.ll?rev=141854&view=auto
>> >>
>> ==============================================================================
>> >> --- llvm/trunk/test/CodeGen/X86/bmi.ll (added)
>> >> +++ llvm/trunk/test/CodeGen/X86/bmi.ll Thu Oct 13 02:09:14 2011
>> >> @@ -0,0 +1,38 @@
>> >> +; RUN: llc < %s -march=x86-64 -mattr=+bmi | FileCheck %s
>> >> +
>> >> +define i32 @t1(i32 %x) nounwind {
>> >> + %tmp = tail call i32 @llvm.cttz.i32( i32 %x )
>> >> + ret i32 %tmp
>> >> +; CHECK: t1:
>> >> +; CHECK: tzcntl
>> >> +}
>> >> +
>> >> +declare i32 @llvm.cttz.i32(i32) nounwind readnone
>> >> +
>> >> +define i16 @t2(i16 %x) nounwind {
>> >> + %tmp = tail call i16 @llvm.cttz.i16( i16 %x )
>> >> + ret i16 %tmp
>> >> +; CHECK: t2:
>> >> +; CHECK: tzcntw
>> >> +}
>> >> +
>> >> +declare i16 @llvm.cttz.i16(i16) nounwind readnone
>> >> +
>> >> +define i64 @t3(i64 %x) nounwind {
>> >> + %tmp = tail call i64 @llvm.cttz.i64( i64 %x )
>> >> + ret i64 %tmp
>> >> +; CHECK: t3:
>> >> +; CHECK: tzcntq
>> >> +}
>> >> +
>> >> +declare i64 @llvm.cttz.i64(i64) nounwind readnone
>> >> +
>> >> +define i8 @t4(i8 %x) nounwind {
>> >> + %tmp = tail call i8 @llvm.cttz.i8( i8 %x )
>> >> + ret i8 %tmp
>> >> +; CHECK: t4:
>> >> +; CHECK: tzcntw
>> >> +}
>> >> +
>> >> +declare i8 @llvm.cttz.i8(i8) nounwind readnone
>> >> +
>> >>
>> >> Modified: llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt
>> >> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt?rev=141854&r1=141853&r2=141854&view=diff
>> >>
>> ==============================================================================
>> >> --- llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt (original)
>> >> +++ llvm/trunk/test/MC/Disassembler/X86/simple-tests.txt Thu Oct 13
>> 02:09:14 2011
>> >> @@ -497,3 +497,12 @@
>> >>
>> >> # CHECK: lzcntq %rax, %rax
>> >> 0xf3 0x48 0x0f 0xbd 0xc0
>> >> +
>> >> +# CHECK: tzcntl %eax, %eax
>> >> +0xf3 0x0f 0xbc 0xc0
>> >> +
>> >> +# CHECK: tzcntw %ax, %ax
>> >> +0x66 0xf3 0x0f 0xbc 0xc0
>> >> +
>> >> +# CHECK: tzcntq %rax, %rax
>> >> +0xf3 0x48 0x0f 0xbc 0xc0
>> >>
>> >> Modified: llvm/trunk/test/MC/Disassembler/X86/x86-32.txt
>> >> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/x86-32.txt?rev=141854&r1=141853&r2=141854&view=diff
>> >>
>> ==============================================================================
>> >> --- llvm/trunk/test/MC/Disassembler/X86/x86-32.txt (original)
>> >> +++ llvm/trunk/test/MC/Disassembler/X86/x86-32.txt Thu Oct 13 02:09:14
>> 2011
>> >> @@ -477,3 +477,9 @@
>> >>
>> >> # CHECK: lzcntw %ax, %ax
>> >> 0x66 0xf3 0x0f 0xbd 0xc0
>> >> +
>> >> +# CHECK: tzcntl %eax, %eax
>> >> +0xf3 0x0f 0xbc 0xc0
>> >> +
>> >> +# CHECK: tzcntw %ax, %ax
>> >> +0x66 0xf3 0x0f 0xbc 0xc0
>> >>
>> >>
>> >> _______________________________________________
>> >> llvm-commits mailing list
>> >> llvm-commits at cs.uiuc.edu
>> >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>> >
>> > _______________________________________________
>> > llvm-commits mailing list
>> > llvm-commits at cs.uiuc.edu
>> > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>>
>>
>
>
> --
> ~Craig
>
>
>
--
~Craig
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20111013/94b8a966/attachment.html>
More information about the llvm-commits
mailing list