[llvm-commits] List concatenation in tblgen

[James Molloy]

Will do, thanks Jakob.

Cheers,

James

-----Original Message-----
From: Jakob Stoklund Olesen [mailto:stoklund at 2pi.dk] 
Sent: 13 October 2011 15:38
To: James Molloy
Cc: <llvm-commits at cs.uiuc.edu>
Subject: Re: [llvm-commits] List concatenation in tblgen

Go for it, but please wait for the 3.0 branch.

/jakob

On Oct 13, 2011, at 5:33 AM, "James Molloy" <james.molloy at arm.com> wrote:

> Hi,
> 
> I've been working on a processor itinerary with a lot of InstrStages - too
> many to really put in each instruction itinerary definition. I wanted to
> create a proper class hierarchy, but that would involve concatenating
lists
> of InstrStages and tablegen doesn't have that functionality.
> 
> I've created a patch to add a !listconcat(x, y) function along the same
> lines as !strconcat. Before I push for internal approval to send this
patch,
> would there be any complaints to my applying it? It allows you to do, for
> example:
> 
> // 2-cycle issue pipeline stage, 2-wide.
> Def Issue00 : FuncUnit;
> Def Issue01 : FuncUnit;
> Def Issue10 : FuncUnit;
> Def Issue11 : FuncUnit;
> 
> Class IssueStage<InstrItinClass Class, list<InstrStage> stages,
>                 list<int> operandcycles = [], list<Bypass> bypasses = []>
>  : InstrItinData<Class,
>                  !listconcat([InstrStage<1, [Issue00,Issue01], 0>,
>                               InstrStage<1, [Issue10,Issue11], 0>],
> stages),
>                  Operandcycles, bypasses>;
> 
> In this example, other classes (such as AddStage, MulStaget, LSStage)
could
> inherit from IssueStage to make it clearer that all itinerary descriptions
> have a 2-wide, 2-cycle fetch/decode/issue stage at the beginning.
> 
> !listconcat is an obviously missing piece of functionality, imho.
> 
> Thoughts?
> 
> Cheers,
> 
> James
> 
> 
> 
> 
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