[llvm-commits] [llvm] r141819 - /llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
Jim Grosbach
grosbach at apple.com
Wed Oct 12 14:59:02 PDT 2011
Author: grosbach
Date: Wed Oct 12 16:59:02 2011
New Revision: 141819
URL: http://llvm.org/viewvc/llvm-project?rev=141819&view=rev
Log:
ARM addrmode5 represents the 'U' bit of the encoding backwards.
The disassembler needs to use the AM5 factory methods instead of just
building up the immediate directly.
Modified:
llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=141819&r1=141818&r2=141819&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Wed Oct 12 16:59:02 2011
@@ -1248,48 +1248,51 @@
case ARM::t2LDC2L_OFFSET:
case ARM::t2LDC2_PRE:
case ARM::t2LDC2L_PRE:
- case ARM::t2LDC2_POST:
- case ARM::t2LDC2L_POST:
case ARM::t2STC2_OFFSET:
case ARM::t2STC2L_OFFSET:
case ARM::t2STC2_PRE:
case ARM::t2STC2L_PRE:
- case ARM::t2STC2_POST:
- case ARM::t2STC2L_POST:
case ARM::LDC2_OFFSET:
case ARM::LDC2L_OFFSET:
case ARM::LDC2_PRE:
case ARM::LDC2L_PRE:
- case ARM::LDC2_POST:
- case ARM::LDC2L_POST:
case ARM::STC2_OFFSET:
case ARM::STC2L_OFFSET:
case ARM::STC2_PRE:
case ARM::STC2L_PRE:
- case ARM::STC2_POST:
- case ARM::STC2L_POST:
case ARM::t2LDC_OFFSET:
case ARM::t2LDCL_OFFSET:
case ARM::t2LDC_PRE:
case ARM::t2LDCL_PRE:
- case ARM::t2LDC_POST:
- case ARM::t2LDCL_POST:
case ARM::t2STC_OFFSET:
case ARM::t2STCL_OFFSET:
case ARM::t2STC_PRE:
case ARM::t2STCL_PRE:
- case ARM::t2STC_POST:
- case ARM::t2STCL_POST:
case ARM::LDC_OFFSET:
case ARM::LDCL_OFFSET:
case ARM::LDC_PRE:
case ARM::LDCL_PRE:
- case ARM::LDC_POST:
- case ARM::LDCL_POST:
case ARM::STC_OFFSET:
case ARM::STCL_OFFSET:
case ARM::STC_PRE:
case ARM::STCL_PRE:
+ imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
+ Inst.addOperand(MCOperand::CreateImm(imm));
+ break;
+ case ARM::t2LDC2_POST:
+ case ARM::t2LDC2L_POST:
+ case ARM::t2STC2_POST:
+ case ARM::t2STC2L_POST:
+ case ARM::LDC2_POST:
+ case ARM::LDC2L_POST:
+ case ARM::STC2_POST:
+ case ARM::STC2L_POST:
+ case ARM::t2LDC_POST:
+ case ARM::t2LDCL_POST:
+ case ARM::t2STC_POST:
+ case ARM::t2STCL_POST:
+ case ARM::LDC_POST:
+ case ARM::LDCL_POST:
case ARM::STC_POST:
case ARM::STCL_POST:
imm |= U << 8;
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