[llvm-commits] [llvm] r141667 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp test/CodeGen/X86/2011-10-11-srl.ll

[Eli Friedman]

2011/10/11 Rotem, Nadav <nadav.rotem at intel.com>:
> Hi Eli,
>
> We are seeing shifts at this point because SIGN_EXTEND_INREG are lowered to vector shifts. Should we handle this elsewhere ?

A vector SIGN_EXTEND_INREG shouldn't make it past LegalizeVectorOps.

-Eli

> Nadav
>
> -----Original Message-----
> From: Eli Friedman [mailto:eli.friedman at gmail.com]
> Sent: Tuesday, October 11, 2011 17:29
> To: Rotem, Nadav
> Cc: llvm-commits at cs.uiuc.edu
> Subject: Re: [llvm-commits] [llvm] r141667 - in /llvm/trunk: lib/CodeGen/SelectionDAG/LegalizeDAG.cpp test/CodeGen/X86/2011-10-11-srl.ll
>
> On Tue, Oct 11, 2011 at 7:36 AM, Nadav Rotem <nadav.rotem at intel.com> wrote:
>> Author: nadav
>> Date: Tue Oct 11 09:36:35 2011
>> New Revision: 141667
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=141667&view=rev
>> Log:
>> Add support for legalization of vector SHL/SRA/SRL instructions
>>
>> Added:
>>    llvm/trunk/test/CodeGen/X86/2011-10-11-srl.ll
>> Modified:
>>    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
>>
>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=141667&r1=141666&r2=141667&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Oct 11 09:36:35 2011
>> @@ -989,6 +989,31 @@
>>  #endif
>>     assert(0 && "Do not know how to legalize this operator!");
>>
>> +  case ISD::SRA:
>> +  case ISD::SRL:
>> +  case ISD::SHL: {
>> +    // Scalarize vector SRA/SRL/SHL.
>> +    EVT VT = Node->getValueType(0);
>> +    assert(VT.isVector() && "Unable to legalize non-vector shift");
>> +    assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
>> +    unsigned NumElem = VT.getVectorNumElements();
>> +
>> +    SmallVector<SDValue, 8> Scalars;
>> +    for (unsigned Idx = 0; Idx < NumElem; Idx++) {
>> +      SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
>> +                               VT.getScalarType(),
>> +                               Node->getOperand(0), DAG.getIntPtrConstant(Idx));
>> +      SDValue Sh = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
>> +                               VT.getScalarType(),
>> +                               Node->getOperand(1), DAG.getIntPtrConstant(Idx));
>> +      Scalars.push_back(DAG.getNode(Node->getOpcode(), dl,
>> +                                    VT.getScalarType(), Ex, Sh));
>> +    }
>> +    Result = DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0),
>> +                         &Scalars[0], Scalars.size());
>> +    break;
>> +  }
>
> If you're still seeing a vector shift at this point, something has
> gone wrong... why is this shift not getting caught by vector
> legalization?
>
> -Eli
>
>> Added: llvm/trunk/test/CodeGen/X86/2011-10-11-srl.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-10-11-srl.ll?rev=141667&view=auto
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/X86/2011-10-11-srl.ll (added)
>> +++ llvm/trunk/test/CodeGen/X86/2011-10-11-srl.ll Tue Oct 11 09:36:35 2011
>> @@ -0,0 +1,11 @@
>> +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -promote-elements -mattr=-sse41
>> +
>> +target triple = "x86_64-unknown-linux-gnu"
>> +
>> +define void @m387(<2 x i8>* %p, <2 x i16>* %q) {
>> +  %t = load <2 x i8>* %p
>> +  %r = sext <2 x i8> %t to <2 x i16>
>> +  store <2 x i16> %r, <2 x i16>* %q
>> +  ret void
>> +}
>> +
>>
>>
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>>
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