[llvm-commits] [llvm] r141500 - /llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp

[Jakob Stoklund Olesen]

On Oct 8, 2011, at 2:25 PM, Cameron Zwarich wrote:

> Could this sort of thing be checked statically?

I wish.

The 20 x86 8-bit registers are crazy. 12 can only be accessed with an REX prefix, and the 4 H-regs can only be accessed without a prefix.

Ideally, GR8_NOREX shouldn't be a sub-class of GR8, and this wouldn't be as big a problem. Unfortunately, GR8 is identical to GR8_NOREX in 32-bit mode, so TableGen considers it a super-class.

We could create separate GR8 register classes for 32-bit and 64-bit modes, but that would require duplicating instruction definitions as well.

Currently, we only use the H-registers at special occasions, and we make sure they are only ever used by *_NOREX instructions. The users are enforcing a register class constraint that really belongs on the COPY instruction, but copies don't support constraints.

The sub-register copy is almost always coalesced away, and the *_NOREX users use the sub_8bit_hi sub-register directly.

The problem is when the COPY isn't coalesced, and the live range might be split.

/jakob


> On Oct 8, 2011, at 1:20 PM, Jakob Stoklund Olesen <stoklund at 2pi.dk> wrote:
> 
>> Author: stoklund
>> Date: Sat Oct  8 15:20:03 2011
>> New Revision: 141500
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=141500&view=rev
>> Log:
>> Prevent potential NOREX bug.
>> 
>> A GR8_NOREX virtual register is created when extrating a sub_8bit_hi
>> sub-register:
>> 
>> %vreg2<def> = COPY %vreg1:sub_8bit_hi; GR8_NOREX:%vreg2 %GR64_ABCD:%vreg1
>> TEST8ri_NOREX %vreg2, 1, %EFLAGS<imp-def>; GR8_NOREX:%vreg2
>> 
>> If such a live range is ever split, its register class must not be
>> inflated to GR8.  The sub-register copy can only target GR8_NOREX.
>> 
>> I dont have a test case for this theoretical bug.
>> 
>> Modified:
>>   llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
>> 
>> Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=141500&r1=141499&r2=141500&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)
>> +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Sat Oct  8 15:20:03 2011
>> @@ -246,6 +246,17 @@
>> 
>> const TargetRegisterClass*
>> X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) const{
>> +  // Don't allow super-classes of GR8_NOREX.  This class is only used after
>> +  // extrating sub_8bit_hi sub-registers.  The H sub-registers cannot be copied
>> +  // to the full GR8 register class in 64-bit mode, so we cannot allow the
>> +  // reigster class inflation.
>> +  //
>> +  // The GR8_NOREX class is always used in a way that won't be constrained to a
>> +  // sub-class, so sub-classes like GR8_ABCD_L are allowed to expand to the
>> +  // full GR8 class.
>> +  if (RC == X86::GR8_NOREXRegisterClass)
>> +    return RC;
>> +
>>  const TargetRegisterClass *Super = RC;
>>  TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
>>  do {
>> 
>> 
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