[llvm-commits] [llvm] r141371 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/2011-05-31-movmsk.ll test/CodeGen/X86/movmsk.ll
Evan Cheng
evan.cheng at apple.com
Fri Oct 7 10:21:44 PDT 2011
Author: evancheng
Date: Fri Oct 7 12:21:44 2011
New Revision: 141371
URL: http://llvm.org/viewvc/llvm-project?rev=141371&view=rev
Log:
High bits of movmskp{s|d} and pmovmskb are known zero. rdar://10247336
Added:
llvm/trunk/test/CodeGen/X86/movmsk.ll
- copied, changed from r141365, llvm/trunk/test/CodeGen/X86/2011-05-31-movmsk.ll
Removed:
llvm/trunk/test/CodeGen/X86/2011-05-31-movmsk.ll
Modified:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=141371&r1=141370&r2=141371&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Oct 7 12:21:44 2011
@@ -12333,6 +12333,33 @@
KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(),
Mask.getBitWidth() - 1);
break;
+ case ISD::INTRINSIC_WO_CHAIN: {
+ unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
+ unsigned NumLoBits = 0;
+ switch (IntId) {
+ default: break;
+ case Intrinsic::x86_sse_movmsk_ps:
+ case Intrinsic::x86_avx_movmsk_ps_256:
+ case Intrinsic::x86_sse2_movmsk_pd:
+ case Intrinsic::x86_avx_movmsk_pd_256:
+ case Intrinsic::x86_mmx_pmovmskb:
+ case Intrinsic::x86_sse2_pmovmskb_128: {
+ // High bits of movmskp{s|d}, pmovmskb are known zero.
+ switch (IntId) {
+ case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break;
+ case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break;
+ case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break;
+ case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break;
+ case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break;
+ case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break;
+ }
+ KnownZero = APInt::getHighBitsSet(Mask.getBitWidth(),
+ Mask.getBitWidth() - NumLoBits);
+ break;
+ }
+ }
+ break;
+ }
}
}
Removed: llvm/trunk/test/CodeGen/X86/2011-05-31-movmsk.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-05-31-movmsk.ll?rev=141370&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2011-05-31-movmsk.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2011-05-31-movmsk.ll (removed)
@@ -1,79 +0,0 @@
-; RUN: llc -mcpu=core2 < %s | FileCheck %s
-; ModuleID = '<stdin>'
-target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
-target triple = "x86_64-apple-macosx10.6.6"
-
-%0 = type { double }
-%union.anon = type { float }
-
-define i32 @double_signbit(double %d1) nounwind uwtable readnone ssp {
-entry:
- %__x.addr.i = alloca double, align 8
- %__u.i = alloca %0, align 8
- %0 = bitcast double* %__x.addr.i to i8*
- %1 = bitcast %0* %__u.i to i8*
- store double %d1, double* %__x.addr.i, align 8
- %__f.i = getelementptr inbounds %0* %__u.i, i64 0, i32 0
- store double %d1, double* %__f.i, align 8
- %tmp = bitcast double %d1 to i64
-; CHECK-NOT: shr
-; CHECK: movmskpd
-; CHECK-NEXT: and
- %tmp1 = lshr i64 %tmp, 63
- %shr.i = trunc i64 %tmp1 to i32
- ret i32 %shr.i
-}
-
-define i32 @double_add_signbit(double %d1, double %d2) nounwind uwtable readnone ssp {
-entry:
- %__x.addr.i = alloca double, align 8
- %__u.i = alloca %0, align 8
- %add = fadd double %d1, %d2
- %0 = bitcast double* %__x.addr.i to i8*
- %1 = bitcast %0* %__u.i to i8*
- store double %add, double* %__x.addr.i, align 8
- %__f.i = getelementptr inbounds %0* %__u.i, i64 0, i32 0
- store double %add, double* %__f.i, align 8
- %tmp = bitcast double %add to i64
-; CHECK-NOT: shr
-; CHECK: movmskpd
-; CHECK-NEXT: and
- %tmp1 = lshr i64 %tmp, 63
- %shr.i = trunc i64 %tmp1 to i32
- ret i32 %shr.i
-}
-
-define i32 @float_signbit(float %f1) nounwind uwtable readnone ssp {
-entry:
- %__x.addr.i = alloca float, align 4
- %__u.i = alloca %union.anon, align 4
- %0 = bitcast float* %__x.addr.i to i8*
- %1 = bitcast %union.anon* %__u.i to i8*
- store float %f1, float* %__x.addr.i, align 4
- %__f.i = getelementptr inbounds %union.anon* %__u.i, i64 0, i32 0
- store float %f1, float* %__f.i, align 4
- %2 = bitcast float %f1 to i32
-; CHECK-NOT: shr
-; CHECK: movmskps
-; CHECK-NEXT: and
- %shr.i = lshr i32 %2, 31
- ret i32 %shr.i
-}
-
-define i32 @float_add_signbit(float %f1, float %f2) nounwind uwtable readnone ssp {
-entry:
- %__x.addr.i = alloca float, align 4
- %__u.i = alloca %union.anon, align 4
- %add = fadd float %f1, %f2
- %0 = bitcast float* %__x.addr.i to i8*
- %1 = bitcast %union.anon* %__u.i to i8*
- store float %add, float* %__x.addr.i, align 4
- %__f.i = getelementptr inbounds %union.anon* %__u.i, i64 0, i32 0
- store float %add, float* %__f.i, align 4
- %2 = bitcast float %add to i32
-; CHECK-NOT: shr
-; CHECK: movmskps
-; CHECK-NEXT: and
- %shr.i = lshr i32 %2, 31
- ret i32 %shr.i
-}
Copied: llvm/trunk/test/CodeGen/X86/movmsk.ll (from r141365, llvm/trunk/test/CodeGen/X86/2011-05-31-movmsk.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/movmsk.ll?p2=llvm/trunk/test/CodeGen/X86/movmsk.ll&p1=llvm/trunk/test/CodeGen/X86/2011-05-31-movmsk.ll&r1=141365&r2=141371&rev=141371&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2011-05-31-movmsk.ll (original)
+++ llvm/trunk/test/CodeGen/X86/movmsk.ll Fri Oct 7 12:21:44 2011
@@ -77,3 +77,34 @@
%shr.i = lshr i32 %2, 31
ret i32 %shr.i
}
+
+; rdar://10247336
+; movmskp{s|d} only set low 4/2 bits, high bits are known zero
+
+define i32 @t1(<4 x float> %x, i32* nocapture %indexTable) nounwind uwtable readonly ssp {
+entry:
+; CHECK: t1:
+; CHECK: movmskps
+; CHECK-NOT: movslq
+ %0 = tail call i32 @llvm.x86.sse.movmsk.ps(<4 x float> %x) nounwind
+ %idxprom = sext i32 %0 to i64
+ %arrayidx = getelementptr inbounds i32* %indexTable, i64 %idxprom
+ %1 = load i32* %arrayidx, align 4
+ ret i32 %1
+}
+
+define i32 @t2(<4 x float> %x, i32* nocapture %indexTable) nounwind uwtable readonly ssp {
+entry:
+; CHECK: t2:
+; CHECK: movmskpd
+; CHECK-NOT: movslq
+ %0 = bitcast <4 x float> %x to <2 x double>
+ %1 = tail call i32 @llvm.x86.sse2.movmsk.pd(<2 x double> %0) nounwind
+ %idxprom = sext i32 %1 to i64
+ %arrayidx = getelementptr inbounds i32* %indexTable, i64 %idxprom
+ %2 = load i32* %arrayidx, align 4
+ ret i32 %2
+}
+
+declare i32 @llvm.x86.sse2.movmsk.pd(<2 x double>) nounwind readnone
+declare i32 @llvm.x86.sse.movmsk.ps(<4 x float>) nounwind readnone
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