[llvm-commits] [llvm] r141353 - in /llvm/trunk: lib/Target/X86/X86InstrInfo.td lib/Target/X86/X86RegisterInfo.td test/MC/X86/x86-32.s test/MC/X86/x86-64.s utils/TableGen/X86DisassemblerTables.cpp

[Eli Friedman]

On Thu, Oct 6, 2011 at 10:35 PM, Craig Topper <craig.topper at gmail.com> wrote:
> Author: ctopper
> Date: Fri Oct  7 00:35:38 2011
> New Revision: 141353
>
> URL: http://llvm.org/viewvc/llvm-project?rev=141353&view=rev
> Log:
> Revert part of r141274. Only need to change encoding for xchg %eax, %eax in 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine.
>
> Modified:
>    llvm/trunk/lib/Target/X86/X86InstrInfo.td
>    llvm/trunk/lib/Target/X86/X86RegisterInfo.td
>    llvm/trunk/test/MC/X86/x86-32.s
>    llvm/trunk/test/MC/X86/x86-64.s
>    llvm/trunk/utils/TableGen/X86DisassemblerTables.cpp
>
> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=141353&r1=141352&r2=141353&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Fri Oct  7 00:35:38 2011
> @@ -1154,11 +1154,15 @@
>                   "xchg{q}\t{$val, $src|$src, $val}", []>;
>  }
>
> -def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16_NOAX:$src),
> +def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
>                   "xchg{w}\t{$src, %ax|AX, $src}", []>, OpSize;
> -def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src),
> -                  "xchg{l}\t{$src, %eax|EAX, $src}", []>;
> -def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64_NOAX:$src),
> +def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
> +                  "xchg{l}\t{$src, %eax|EAX, $src}", []>, Requires<[In32BitMode]>;
> +// Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding.
> +// xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP.
> +def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src),
> +                   "xchg{l}\t{$src, %eax|EAX, $src}", []>, Requires<[In64BitMode]>;
> +def XCHG64ar : RI<0x90, AddRegFrm, (outs), (ins GR64:$src),
>                   "xchg{q}\t{$src, %rax|RAX, $src}", []>;
>
>
> @@ -1716,6 +1720,7 @@
>  def : InstAlias<"xchgq $mem, $val", (XCHG64rm GR64:$val, i64mem:$mem)>;
>
>  // xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms.
> -def : InstAlias<"xchgw %ax, $src", (XCHG16ar GR16_NOAX:$src)>;
> -def : InstAlias<"xchgl %eax, $src", (XCHG32ar GR32_NOAX:$src)>;
> -def : InstAlias<"xchgq %rax, $src", (XCHG64ar GR64_NOAX:$src)>;
> +def : InstAlias<"xchgw %ax, $src", (XCHG16ar GR16:$src)>;
> +def : InstAlias<"xchgl %eax, $src", (XCHG32ar GR32:$src)>, Requires<[In32BitMode]>;
> +def : InstAlias<"xchgl %eax, $src", (XCHG32ar64 GR32_NOAX:$src)>, Requires<[In64BitMode]>;
> +def : InstAlias<"xchgq %rax, $src", (XCHG64ar GR64:$src)>;
>
> Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.td?rev=141353&r1=141352&r2=141353&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86RegisterInfo.td (original)
> +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.td Fri Oct  7 00:35:38 2011
> @@ -390,21 +390,11 @@
>                        (GR32_NOREX sub_32bit)];
>  }
>
> -// GR16_NOAX - GR16 registers except AX.
> -def GR16_NOAX : RegisterClass<"X86", [i16], 16, (sub GR16, AX)> {
> -  let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi)];
> -}
> -
> -// GR32_NOAX - GR32 registers except EAX.
> +// GR32_NOAX - GR32 registers except EAX. Used by AddRegFrm of XCHG32 in 64-bit
> +// mode to prevent encoding using the 0x90 NOP encoding. xchg %eax, %eax needs
> +// to clear upper 32-bits of RAX so is not a NOP.
>  def GR32_NOAX : RegisterClass<"X86", [i32], 32, (sub GR32, EAX)> {
> -  let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi), (GR16_NOAX sub_16bit)];
> -}
> -
> -// GR64_NOAX - GR64 registers except RAX.
> -def GR64_NOAX : RegisterClass<"X86", [i64], 64, (sub GR64, RAX)> {
> -  let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi),
> -                       (GR16_NOAX sub_16bit),
> -                       (GR32_NOAX sub_32bit)];
> +  let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi), (GR16 sub_16bit)];
>  }
>
>  // GR32_NOSP - GR32 registers except ESP.
>
> Modified: llvm/trunk/test/MC/X86/x86-32.s
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-32.s?rev=141353&r1=141352&r2=141353&view=diff
> ==============================================================================
> --- llvm/trunk/test/MC/X86/x86-32.s (original)
> +++ llvm/trunk/test/MC/X86/x86-32.s Fri Oct  7 00:35:38 2011
> @@ -948,11 +948,11 @@
>
>  // PR10345
>  // CHECK: xchgl %eax, %eax
> -// CHECK: encoding: [0x87,0xc0]
> +// CHECK: encoding: [0x90]
>  xchgl %eax, %eax
>
>  // CHECK: xchgw %ax, %ax
> -// CHECK: encoding: [0x66,0x87,0xc0]
> +// CHECK: encoding: [0x66,0x90]
>  xchgw %ax, %ax
>
>  // CHECK: xchgl %ecx, %eax
>
> Modified: llvm/trunk/test/MC/X86/x86-64.s
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-64.s?rev=141353&r1=141352&r2=141353&view=diff
> ==============================================================================
> --- llvm/trunk/test/MC/X86/x86-64.s (original)
> +++ llvm/trunk/test/MC/X86/x86-64.s Fri Oct  7 00:35:38 2011
> @@ -1173,7 +1173,7 @@
>
>  // PR10345
>  // CHECK: xchgq %rax, %rax
> -// CHECK: encoding: [0x48,0x87,0xc0]
> +// CHECK: encoding: [0x48,0x90]
>  xchgq %rax, %rax
>
>  // CHECK: xchgl %eax, %eax
> @@ -1181,7 +1181,7 @@
>  xchgl %eax, %eax
>
>  // CHECK: xchgw %ax, %ax
> -// CHECK: encoding: [0x66,0x87,0xc0]
> +// CHECK: encoding: [0x66,0x90]
>  xchgw %ax, %ax

Close, but not quite: 0x66 0x90 is a NOP, not xchgw on x86-64.

-Eli