[llvm-commits] [llvm] r141258 - in /llvm/trunk: include/llvm/Target/TargetRegisterInfo.h utils/TableGen/RegisterInfoEmitter.cpp

[Jakob Stoklund Olesen]

Author: stoklund
Date: Wed Oct  5 19:08:27 2011
New Revision: 141258

URL: http://llvm.org/viewvc/llvm-project?rev=141258&view=rev
Log:
Remove the TRI::getSubRegisterRegClass() hook.

This restores my karma after I added TRI::getSubClassWithSubReg().

Register constraints are applied 'backwards'.  Starting from the
register class required by an instruction operand, the correct question
is: 'How can I constrain the super-register register class so all its
sub-registers satisfy the instruction constraint?' The
getMatchingSuperRegClass() hook answers that.

We never need to go 'forwards': Starting from a super-register register
class, what register class are the sub-registers in?  The
getSubRegisterRegClass() hook did that.

Modified:
    llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
    llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp

Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=141258&r1=141257&r2=141258&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Wed Oct  5 19:08:27 2011
@@ -42,16 +42,14 @@
   const vt_iterator VTs;
   const unsigned *SubClassMask;
   const sc_iterator SuperClasses;
-  const sc_iterator SubRegClasses;
   const sc_iterator SuperRegClasses;
 public:
   TargetRegisterClass(const MCRegisterClass *MC, const EVT *vts,
                       const unsigned *subcm,
                       const TargetRegisterClass * const *supcs,
-                      const TargetRegisterClass * const *subregcs,
                       const TargetRegisterClass * const *superregcs)
     : MC(MC), VTs(vts), SubClassMask(subcm), SuperClasses(supcs),
-      SubRegClasses(subregcs), SuperRegClasses(superregcs) {}
+      SuperRegClasses(superregcs) {}
 
   virtual ~TargetRegisterClass() {}     // Allow subclasses
 
@@ -127,25 +125,6 @@
     return I;
   }
 
-  /// subregclasses_begin / subregclasses_end - Loop over all of
-  /// the subreg register classes of this register class.
-  sc_iterator subregclasses_begin() const {
-    return SubRegClasses;
-  }
-
-  sc_iterator subregclasses_end() const {
-    sc_iterator I = SubRegClasses;
-    while (*I != NULL) ++I;
-    return I;
-  }
-
-  /// getSubRegisterRegClass - Return the register class of subregisters with
-  /// index SubIdx, or NULL if no such class exists.
-  const TargetRegisterClass* getSubRegisterRegClass(unsigned SubIdx) const {
-    assert(SubIdx>0 && "Invalid subregister index");
-    return SubRegClasses[SubIdx-1];
-  }
-
   /// superregclasses_begin / superregclasses_end - Loop over all of
   /// the superreg register classes of this register class.
   sc_iterator superregclasses_begin() const {

Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=141258&r1=141257&r2=141258&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Wed Oct  5 19:08:27 2011
@@ -543,40 +543,17 @@
     unsigned NumSubRegIndices = RegBank.getSubRegIndices().size();
 
     if (NumSubRegIndices) {
-      // Emit the sub-register classes for each RegisterClass
+      // Compute the super-register classes for each RegisterClass
       for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
         const CodeGenRegisterClass &RC = *RegisterClasses[rc];
-        std::vector<Record*> SRC(NumSubRegIndices);
         for (DenseMap<Record*,Record*>::const_iterator
              i = RC.SubRegClasses.begin(),
              e = RC.SubRegClasses.end(); i != e; ++i) {
-          // Build SRC array.
-          unsigned idx = RegBank.getSubRegIndexNo(i->first);
-          SRC.at(idx-1) = i->second;
-
           // Find the register class number of i->second for SuperRegClassMap.
           const CodeGenRegisterClass *RC2 = RegBank.getRegClass(i->second);
           assert(RC2 && "Invalid register class in SubRegClasses");
           SuperRegClassMap[RC2->EnumValue].insert(rc);
         }
-
-        // Give the register class a legal C name if it's anonymous.
-        std::string Name = RC.getName();
-
-        OS << "  // " << Name
-           << " Sub-register Classes...\n"
-           << "  static const TargetRegisterClass* const "
-           << Name << "SubRegClasses[] = {\n    ";
-
-        for (unsigned idx = 0; idx != NumSubRegIndices; ++idx) {
-          if (idx)
-            OS << ", ";
-          if (SRC[idx])
-            OS << "&" << getQualifiedName(SRC[idx]) << "RegClass";
-          else
-            OS << "0";
-        }
-        OS << "\n  };\n\n";
       }
 
       // Emit the super-register classes for each RegisterClass
@@ -651,9 +628,7 @@
         OS << "NullRegClasses, ";
       else
         OS << RC.getName() + "Superclasses, ";
-      OS << (NumSubRegIndices ? RC.getName() + "Sub" : std::string("Null"))
-         << "RegClasses, "
-         << (NumSubRegIndices ? RC.getName() + "Super" : std::string("Null"))
+      OS << (NumSubRegIndices ? RC.getName() + "Super" : std::string("Null"))
          << "RegClasses"
          << ") {}\n";
       if (!RC.AltOrderSelect.empty()) {