[llvm-commits] [llvm] r141247 - in /llvm/trunk: lib/Target/ARM/ARMISelDAGToDAG.cpp test/CodeGen/ARM/shifter_operand.ll

[Cameron Zwarich]

Author: zwarich
Date: Wed Oct  5 18:38:50 2011
New Revision: 141247

URL: http://llvm.org/viewvc/llvm-project?rev=141247&view=rev
Log:
Remove a check from ARM shifted operand isel helper methods, which were blocking
merging an lsl #2 that has multiple uses on A9. This shift is free, so there is
no problem merging it in multiple places. Other unprofitable shifts will not be
merged.

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
    llvm/trunk/test/CodeGen/ARM/shifter_operand.ll

Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=141247&r1=141246&r2=141247&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Wed Oct  5 18:38:50 2011
@@ -519,11 +519,6 @@
       return false;
   }
 
-  if (Subtarget->isCortexA9() && !N.hasOneUse()) {
-    // Compute R +/- (R << N) and reuse it.
-    return false;
-  }
-
   // Otherwise this is R +/- [possibly shifted] R.
   ARM_AM::AddrOpc AddSub = N.getOpcode() == ISD::SUB ? ARM_AM::sub:ARM_AM::add;
   ARM_AM::ShiftOpc ShOpcVal =
@@ -1286,11 +1281,6 @@
       return false;
   }
 
-  if (Subtarget->isCortexA9() && !N.hasOneUse()) {
-    // Compute R + (R << [1,2,3]) and reuse it.
-    return false;
-  }
-
   // Look for (R + R) or (R + (R << [1,2,3])).
   unsigned ShAmt = 0;
   Base   = N.getOperand(0);

Modified: llvm/trunk/test/CodeGen/ARM/shifter_operand.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/shifter_operand.ll?rev=141247&r1=141246&r2=141247&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/shifter_operand.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/shifter_operand.ll Wed Oct  5 18:38:50 2011
@@ -54,13 +54,12 @@
 define fastcc void @test4(i16 %addr) nounwind {
 entry:
 ; A8: test4:
-; A8: ldr r2, [r0, r1, lsl #2]
-; A8: str r2, [r0, r1, lsl #2]
+; A8: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]
+; A8: str [[REG]], [r0, r1, lsl #2]
 
 ; A9: test4:
-; A9: add r0, r0, r{{[0-9]+}}, lsl #2
-; A9: ldr r1, [r0]
-; A9: str r1, [r0]
+; A9: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]
+; A9: str [[REG]], [r0, r1, lsl #2]
   %0 = tail call i8* (...)* @malloc(i32 undef) nounwind
   %1 = bitcast i8* %0 to i32*
   %2 = sext i16 %addr to i32