[llvm-commits] [llvm] r141194 - /llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp

[Akira Hatanaka]

Author: ahatanak
Date: Wed Oct  5 13:11:44 2011
New Revision: 141194

URL: http://llvm.org/viewvc/llvm-project?rev=141194&view=rev
Log:
Add RA to the set of registers that are defined if instruction is a call.


Modified:
    llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp

Modified: llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp?rev=141194&r1=141193&r2=141194&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp Wed Oct  5 13:11:44 2011
@@ -218,13 +218,13 @@
                             SmallSet<unsigned, 32>& RegDefs,
                             SmallSet<unsigned, 32>& RegUses) {
   // If MI is a call or return, just examine the explicit non-variadic operands.
-  // NOTE: $ra is not added to RegDefs, since currently $ra is reserved and
-  //       no instruction that can possibly be put in a delay slot can read or
-  //       write it.
-
   MCInstrDesc MCID = MI->getDesc();
   unsigned e = MCID.isCall() || MCID.isReturn() ? MCID.getNumOperands() :
                                                   MI->getNumOperands();
+  
+  // Add RA to RegDefs to prevent users of RA from going into delay slot. 
+  if (MCID.isCall())
+    RegDefs.insert(Mips::RA);
 
   for (unsigned i = 0; i != e; ++i) {
     const MachineOperand &MO = MI->getOperand(i);