[llvm-commits] [llvm] r140898 - in /llvm/trunk: include/llvm/Target/TargetRegisterInfo.h lib/Target/ARM/ARMBaseRegisterInfo.cpp lib/Target/TargetRegisterInfo.cpp lib/Target/X86/X86RegisterInfo.cpp utils/TableGen/RegisterInfoEmitter.cpp
Jakob Stoklund Olesen
stoklund at 2pi.dk
Fri Sep 30 15:19:07 PDT 2011
Author: stoklund
Date: Fri Sep 30 17:19:07 2011
New Revision: 140898
URL: http://llvm.org/viewvc/llvm-project?rev=140898&view=rev
Log:
Store sub-class lists as a bit vector.
This uses less memory and it reduces the complexity of sub-class
operations:
- hasSubClassEq() and friends become O(1) instead of O(N).
- getCommonSubClass() becomes O(N) instead of O(N^2).
In the future, TableGen will infer register classes. This makes it
cheap to add them.
Modified:
llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
llvm/trunk/lib/Target/TargetRegisterInfo.cpp
llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=140898&r1=140897&r2=140898&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Fri Sep 30 17:19:07 2011
@@ -40,17 +40,17 @@
private:
const MCRegisterClass *MC;
const vt_iterator VTs;
- const sc_iterator SubClasses;
+ const unsigned *SubClassMask;
const sc_iterator SuperClasses;
const sc_iterator SubRegClasses;
const sc_iterator SuperRegClasses;
public:
TargetRegisterClass(const MCRegisterClass *MC, const EVT *vts,
- const TargetRegisterClass * const *subcs,
+ const unsigned *subcm,
const TargetRegisterClass * const *supcs,
const TargetRegisterClass * const *subregcs,
const TargetRegisterClass * const *superregcs)
- : MC(MC), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
+ : MC(MC), VTs(vts), SubClassMask(subcm), SuperClasses(supcs),
SubRegClasses(subregcs), SuperRegClasses(superregcs) {}
virtual ~TargetRegisterClass() {} // Allow subclasses
@@ -159,57 +159,42 @@
}
/// hasSubClass - return true if the specified TargetRegisterClass
- /// is a proper subset of this TargetRegisterClass.
- bool hasSubClass(const TargetRegisterClass *cs) const {
- for (int i = 0; SubClasses[i] != NULL; ++i)
- if (SubClasses[i] == cs)
- return true;
- return false;
+ /// is a proper sub-class of this TargetRegisterClass.
+ bool hasSubClass(const TargetRegisterClass *RC) const {
+ return RC != this && hasSubClassEq(RC);
}
- /// hasSubClassEq - Returns true if RC is a subclass of or equal to this
+ /// hasSubClassEq - Returns true if RC is a sub-class of or equal to this
/// class.
bool hasSubClassEq(const TargetRegisterClass *RC) const {
- return RC == this || hasSubClass(RC);
- }
-
- /// subclasses_begin / subclasses_end - Loop over all of the classes
- /// that are proper subsets of this register class.
- sc_iterator subclasses_begin() const {
- return SubClasses;
- }
-
- sc_iterator subclasses_end() const {
- sc_iterator I = SubClasses;
- while (*I != NULL) ++I;
- return I;
+ unsigned ID = RC->getID();
+ return (SubClassMask[ID / 32] >> (ID % 32)) & 1;
}
/// hasSuperClass - return true if the specified TargetRegisterClass is a
- /// proper superset of this TargetRegisterClass.
- bool hasSuperClass(const TargetRegisterClass *cs) const {
- for (int i = 0; SuperClasses[i] != NULL; ++i)
- if (SuperClasses[i] == cs)
- return true;
- return false;
+ /// proper super-class of this TargetRegisterClass.
+ bool hasSuperClass(const TargetRegisterClass *RC) const {
+ return RC->hasSubClass(this);
}
- /// hasSuperClassEq - Returns true if RC is a superclass of or equal to this
+ /// hasSuperClassEq - Returns true if RC is a super-class of or equal to this
/// class.
bool hasSuperClassEq(const TargetRegisterClass *RC) const {
- return RC == this || hasSuperClass(RC);
+ return RC->hasSubClassEq(this);
}
- /// superclasses_begin / superclasses_end - Loop over all of the classes
- /// that are proper supersets of this register class.
- sc_iterator superclasses_begin() const {
- return SuperClasses;
+ /// getSubClassMask - Returns a bit vector of subclasses, including this one.
+ /// The vector is indexed by class IDs, see hasSubClassEq() above for how to
+ /// use it.
+ const unsigned *getSubClassMask() const {
+ return SubClassMask;
}
- sc_iterator superclasses_end() const {
- sc_iterator I = SuperClasses;
- while (*I != NULL) ++I;
- return I;
+ /// getSuperClasses - Returns a NULL terminated list of super-classes. The
+ /// classes are ordered by ID which is also a topological ordering from large
+ /// to small classes. The list does NOT include the current class.
+ sc_iterator getSuperClasses() const {
+ return SuperClasses;
}
/// isASubClass - return true if this TargetRegisterClass is a subset
Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=140898&r1=140897&r2=140898&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Fri Sep 30 17:19:07 2011
@@ -353,7 +353,7 @@
ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC)
const {
const TargetRegisterClass *Super = RC;
- TargetRegisterClass::sc_iterator I = RC->superclasses_begin();
+ TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
do {
switch (Super->getID()) {
case ARM::GPRRegClassID:
Modified: llvm/trunk/lib/Target/TargetRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetRegisterInfo.cpp?rev=140898&r1=140897&r2=140898&view=diff
==============================================================================
--- llvm/trunk/lib/Target/TargetRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/TargetRegisterInfo.cpp Fri Sep 30 17:19:07 2011
@@ -100,42 +100,23 @@
const TargetRegisterClass *
TargetRegisterInfo::getCommonSubClass(const TargetRegisterClass *A,
const TargetRegisterClass *B) const {
- // First take care of the trivial cases
+ // First take care of the trivial cases.
if (A == B)
return A;
if (!A || !B)
return 0;
- // If B is a subclass of A, it will be handled in the loop below
- if (B->hasSubClass(A))
- return A;
-
- const TargetRegisterClass *Best = 0;
- for (TargetRegisterClass::sc_iterator I = A->subclasses_begin();
- const TargetRegisterClass *X = *I; ++I) {
- if (X == B)
- return B; // B is a subclass of A
-
- // X must be a common subclass of A and B
- if (!B->hasSubClass(X))
- continue;
-
- // A superclass is definitely better.
- if (!Best || Best->hasSuperClass(X)) {
- Best = X;
- continue;
- }
-
- // A subclass is definitely worse
- if (Best->hasSubClass(X))
- continue;
+ // Register classes are ordered topologically, so the largest common
+ // sub-class it the common sub-class with the smallest ID.
+ const unsigned *SubA = A->getSubClassMask();
+ const unsigned *SubB = B->getSubClassMask();
+
+ // We could start the search from max(A.ID, B.ID), but we are only going to
+ // execute 2-3 iterations anyway.
+ for (unsigned Base = 0, BaseE = getNumRegClasses(); Base < BaseE; Base += 32)
+ if (unsigned Common = *SubA++ & *SubB++)
+ return getRegClass(Base + CountTrailingZeros_32(Common));
- // Best and *I have no super/sub class relation - pick the larger class, or
- // the smaller spill size.
- int nb = std::distance(Best->begin(), Best->end());
- int ni = std::distance(X->begin(), X->end());
- if (ni>nb || (ni==nb && X->getSize() < Best->getSize()))
- Best = X;
- }
- return Best;
+ // No common sub-class exists.
+ return NULL;
}
Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=140898&r1=140897&r2=140898&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Fri Sep 30 17:19:07 2011
@@ -235,7 +235,7 @@
const TargetRegisterClass*
X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) const{
const TargetRegisterClass *Super = RC;
- TargetRegisterClass::sc_iterator I = RC->superclasses_begin();
+ TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
do {
switch (Super->getID()) {
case X86::GR8RegClassID:
Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=140898&r1=140897&r2=140898&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Fri Sep 30 17:19:07 2011
@@ -622,26 +622,9 @@
// Give the register class a legal C name if it's anonymous.
std::string Name = RC.TheDef->getName();
- OS << " // " << Name
- << " Register Class sub-classes...\n"
- << " static const TargetRegisterClass* const "
- << Name << "Subclasses[] = {\n ";
-
- bool Empty = true;
- for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
- const CodeGenRegisterClass &RC2 = *RegisterClasses[rc2];
-
- // Sub-classes are used to determine if a virtual register can be used
- // as an instruction operand, or if it must be copied first.
- if (rc == rc2 || !RC.hasSubClass(&RC2)) continue;
-
- if (!Empty) OS << ", ";
- OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
- Empty = false;
- }
-
- OS << (!Empty ? ", " : "") << "NULL";
- OS << "\n };\n\n";
+ OS << " static const unsigned " << Name << "SubclassMask[] = { ";
+ printBitVectorAsHex(OS, RC.getSubClasses(), 32);
+ OS << "};\n\n";
}
// Emit NULL terminated super-class lists.
@@ -668,7 +651,7 @@
<< Target.getName() << "MCRegisterClasses["
<< RC.getName() + "RegClassID" << "], "
<< RC.getName() + "VTs" << ", "
- << RC.getName() + "Subclasses" << ", ";
+ << RC.getName() + "SubclassMask" << ", ";
if (RC.getSuperClasses().empty())
OS << "NullRegClasses, ";
else
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