[llvm-commits] [llvm] r140860 - in /llvm/trunk/test/CodeGen/Mips: mips64instrs.ll mips64shift.ll

[Akira Hatanaka]

Author: ahatanak
Date: Fri Sep 30 12:19:21 2011
New Revision: 140860

URL: http://llvm.org/viewvc/llvm-project?rev=140860&view=rev
Log:
Check values of immediate operands.

Modified:
    llvm/trunk/test/CodeGen/Mips/mips64instrs.ll
    llvm/trunk/test/CodeGen/Mips/mips64shift.ll

Modified: llvm/trunk/test/CodeGen/Mips/mips64instrs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mips64instrs.ll?rev=140860&r1=140859&r2=140860&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/mips64instrs.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/mips64instrs.ll Fri Sep 30 12:19:21 2011
@@ -37,35 +37,35 @@
 
 define i64 @f7(i64 %a0) nounwind readnone {
 entry:
-; CHECK: daddiu
+; CHECK: daddiu ${{[0-9]+}}, ${{[0-9]+}}, 20
   %add = add nsw i64 %a0, 20
   ret i64 %add
 }
 
 define i64 @f8(i64 %a0) nounwind readnone {
 entry:
-; CHECK: daddiu
+; CHECK: daddiu ${{[0-9]+}}, ${{[0-9]+}}, -20
   %sub = add nsw i64 %a0, -20
   ret i64 %sub
 }
 
 define i64 @f9(i64 %a0) nounwind readnone {
 entry:
-; CHECK: andi
+; CHECK: andi ${{[0-9]+}}, ${{[0-9]+}}, 20
   %and = and i64 %a0, 20
   ret i64 %and
 }
 
 define i64 @f10(i64 %a0) nounwind readnone {
 entry:
-; CHECK: ori
+; CHECK: ori ${{[0-9]+}}, ${{[0-9]+}}, 20
   %or = or i64 %a0, 20
   ret i64 %or
 }
 
 define i64 @f11(i64 %a0) nounwind readnone {
 entry:
-; CHECK: xori
+; CHECK: xori ${{[0-9]+}}, ${{[0-9]+}}, 20
   %xor = xor i64 %a0, 20
   ret i64 %xor
 }

Modified: llvm/trunk/test/CodeGen/Mips/mips64shift.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mips64shift.ll?rev=140860&r1=140859&r2=140860&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/mips64shift.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/mips64shift.ll Fri Sep 30 12:19:21 2011
@@ -23,42 +23,42 @@
 
 define i64 @f3(i64 %a0) nounwind readnone {
 entry:
-; CHECK: dsll
+; CHECK: dsll ${{[0-9]+}}, ${{[0-9]+}}, 10
   %shl = shl i64 %a0, 10
   ret i64 %shl
 }
 
 define i64 @f4(i64 %a0) nounwind readnone {
 entry:
-; CHECK: dsra
+; CHECK: dsra ${{[0-9]+}}, ${{[0-9]+}}, 10
   %shr = ashr i64 %a0, 10
   ret i64 %shr
 }
 
 define i64 @f5(i64 %a0) nounwind readnone {
 entry:
-; CHECK: dsrl
+; CHECK: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 10
   %shr = lshr i64 %a0, 10
   ret i64 %shr
 }
 
 define i64 @f6(i64 %a0) nounwind readnone {
 entry:
-; CHECK: dsll32
+; CHECK: dsll32 ${{[0-9]+}}, ${{[0-9]+}}, 8
   %shl = shl i64 %a0, 40
   ret i64 %shl
 }
 
 define i64 @f7(i64 %a0) nounwind readnone {
 entry:
-; CHECK: dsra32
+; CHECK: dsra32 ${{[0-9]+}}, ${{[0-9]+}}, 8
   %shr = ashr i64 %a0, 40
   ret i64 %shr
 }
 
 define i64 @f8(i64 %a0) nounwind readnone {
 entry:
-; CHECK: dsrl32
+; CHECK: dsrl32 ${{[0-9]+}}, ${{[0-9]+}}, 8
   %shr = lshr i64 %a0, 40
   ret i64 %shr
 }