[llvm-commits] [llvm] r140839 - in /llvm/trunk: lib/Target/Mips/Mips64InstrInfo.td test/CodeGen/Mips/mips64instrs.ll

[Akira Hatanaka]

Author: ahatanak
Date: Thu Sep 29 21:08:54 2011
New Revision: 140839

URL: http://llvm.org/viewvc/llvm-project?rev=140839&view=rev
Log:
Mips64 arithmetic and logical instructions with one source register and
immediate.

Modified:
    llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
    llvm/trunk/test/CodeGen/Mips/mips64instrs.ll

Modified: llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td?rev=140839&r1=140838&r2=140839&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips64InstrInfo.td Thu Sep 29 21:08:54 2011
@@ -18,6 +18,18 @@
 def HasMips64r2  : Predicate<"Subtarget.hasMips64r2()">;
 
 //===----------------------------------------------------------------------===//
+// Mips Operand, Complex Patterns and Transformations Definitions.
+//===----------------------------------------------------------------------===//
+
+// Instruction operand types
+def simm16_64      : Operand<i64>;
+
+// Unsigned Operand
+def uimm16_64      : Operand<i64> {
+  let PrintMethod = "printUnsignedImm";
+}
+
+//===----------------------------------------------------------------------===//
 // Instructions specific format
 //===----------------------------------------------------------------------===//
 
@@ -30,6 +42,13 @@
   let isCommutable = isComm;
 }
 
+// Arithmetic 2 register operands
+class ArithI64<bits<6> op, string instr_asm, SDNode OpNode,
+               Operand Od, PatLeaf imm_type> :
+  FI<op, (outs CPU64Regs:$dst), (ins CPU64Regs:$b, Od:$c),
+     !strconcat(instr_asm, "\t$dst, $b, $c"),
+     [(set CPU64Regs:$dst, (OpNode CPU64Regs:$b, imm_type:$c))], IIAlu>;
+
 //  Logical
 let isCommutable = 1 in
 class LogicR64<bits<6> func, string instr_asm, SDNode OpNode>:
@@ -37,10 +56,21 @@
      !strconcat(instr_asm, "\t$dst, $b, $c"),
      [(set CPU64Regs:$dst, (OpNode CPU64Regs:$b, CPU64Regs:$c))], IIAlu>;
 
+class LogicI64<bits<6> op, string instr_asm, SDNode OpNode>:
+  FI<op, (outs CPU64Regs:$dst), (ins CPU64Regs:$b, uimm16_64:$c),
+     !strconcat(instr_asm, "\t$dst, $b, $c"),
+     [(set CPU64Regs:$dst, (OpNode CPU64Regs:$b, immZExt16:$c))], IIAlu>;
+
 //===----------------------------------------------------------------------===//
 // Instruction definition
 //===----------------------------------------------------------------------===//
 
+/// Arithmetic Instructions (ALU Immediate)
+def DADDiu   : ArithI64<0x19, "daddiu", add, simm16_64, immSExt16>;
+def DANDi    : LogicI64<0x0c, "andi", and>;
+def DORi     : LogicI64<0x0d, "ori",  or>;
+def DXORi    : LogicI64<0x0e, "xori",  xor>;
+
 /// Arithmetic Instructions (3-Operand, R-Type)
 def DADDu    : ArithR64<0x00, 0x2d, "daddu", add, IIAlu, 1>;
 def DSUBu    : ArithR64<0x00, 0x2f, "dsubu", sub, IIAlu, 1>;

Modified: llvm/trunk/test/CodeGen/Mips/mips64instrs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mips64instrs.ll?rev=140839&r1=140838&r2=140839&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/mips64instrs.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/mips64instrs.ll Thu Sep 29 21:08:54 2011
@@ -34,3 +34,39 @@
   %xor = xor i64 %a1, %a0
   ret i64 %xor
 }
+
+define i64 @f7(i64 %a0) nounwind readnone {
+entry:
+; CHECK: daddiu
+  %add = add nsw i64 %a0, 20
+  ret i64 %add
+}
+
+define i64 @f8(i64 %a0) nounwind readnone {
+entry:
+; CHECK: daddiu
+  %sub = add nsw i64 %a0, -20
+  ret i64 %sub
+}
+
+define i64 @f9(i64 %a0) nounwind readnone {
+entry:
+; CHECK: andi
+  %and = and i64 %a0, 20
+  ret i64 %and
+}
+
+define i64 @f10(i64 %a0) nounwind readnone {
+entry:
+; CHECK: ori
+  %or = or i64 %a0, 20
+  ret i64 %or
+}
+
+define i64 @f11(i64 %a0) nounwind readnone {
+entry:
+; CHECK: xori
+  %xor = xor i64 %a0, 20
+  ret i64 %xor
+}
+