[llvm-commits] [llvm] r140463 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Nadav Rotem
nadav.rotem at intel.com
Sat Sep 24 11:32:19 PDT 2011
Author: nadav
Date: Sat Sep 24 13:32:19 2011
New Revision: 140463
URL: http://llvm.org/viewvc/llvm-project?rev=140463&view=rev
Log:
[Vector-Select] Address one of the problems in 10902.
When generating the trunc-store of i1's, we need to use the vector type and not
the scalar type.
This patch fixes the assertion in CodeGen/Generic/bool-vector.ll when
running with -promote-elements.
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=140463&r1=140462&r2=140463&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sat Sep 24 13:32:19 2011
@@ -1180,6 +1180,10 @@
// bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
unsigned NewWidth = SrcVT.getStoreSizeInBits();
EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth);
+ if (SrcVT.isVector()) {
+ NVT = EVT::getVectorVT(*DAG.getContext(), NVT,
+ SrcVT.getVectorNumElements());
+ }
SDValue Ch;
// The extra bits are guaranteed to be zero, since we stored them that
@@ -1521,7 +1525,12 @@
// TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
StVT.getStoreSizeInBits());
- Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT);
+ if (StVT.isVector()) {
+ NVT = EVT::getVectorVT(*DAG.getContext(), NVT,
+ StVT.getVectorNumElements());
+ }
+
+ Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT.getScalarType());
Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(),
NVT, isVolatile, isNonTemporal, Alignment);
} else if (StWidth & (StWidth - 1)) {
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