[llvm-commits] [llvm] r140443 - in /llvm/trunk: .gitignore lib/Target/Mips/MipsISelLowering.cpp lib/Target/Mips/MipsInstrInfo.td

[Akira Hatanaka]

Author: ahatanak
Date: Fri Sep 23 20:34:44 2011
New Revision: 140443

URL: http://llvm.org/viewvc/llvm-project?rev=140443&view=rev
Log:
Preparation for adding simple Mips64 instructions.

Modified:
    llvm/trunk/.gitignore
    llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
    llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

Modified: llvm/trunk/.gitignore
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/.gitignore?rev=140443&r1=140442&r2=140443&view=diff
==============================================================================
--- llvm/trunk/.gitignore (original)
+++ llvm/trunk/.gitignore Fri Sep 23 20:34:44 2011
@@ -17,11 +17,13 @@
 *.pyc
 # vim swap files
 .*.swp
+*.patch
 
 #==============================================================================#
 # Explicit files to ignore (only matches one).
 #==============================================================================#
 .gitusers
+.svn
 autom4te.cache
 cscope.files
 cscope.out

Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=140443&r1=140442&r2=140443&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Fri Sep 23 20:34:44 2011
@@ -95,6 +95,9 @@
   addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
   addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
 
+  if (HasMips64)
+    addRegisterClass(MVT::i64, Mips::CPU64RegsRegisterClass);
+
   // When dealing with single precision only, use libcalls
   if (!Subtarget->isSingleFloat()) {
     if (HasMips64)
@@ -2260,6 +2263,8 @@
 
       if (RegVT == MVT::i32)
         RC = Mips::CPURegsRegisterClass;
+      else if (RegVT == MVT::i64)
+        RC = Mips::CPU64RegsRegisterClass;
       else if (RegVT == MVT::f32)
         RC = Mips::FGR32RegisterClass;
       else if (RegVT == MVT::f64) {

Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=140443&r1=140442&r2=140443&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Fri Sep 23 20:34:44 2011
@@ -879,4 +879,5 @@
 //===----------------------------------------------------------------------===//
 
 include "MipsInstrFPU.td"
+include "Mips64InstrInfo.td"