[llvm-commits] [llvm] r140294 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

[Benjamin Kramer]

Author: d0k
Date: Wed Sep 21 22:01:42 2011
New Revision: 140294

URL: http://llvm.org/viewvc/llvm-project?rev=140294&view=rev
Log:
X86: Don't form min/max nodes if the target is missing SSE.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=140294&r1=140293&r2=140294&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Sep 21 22:01:42 2011
@@ -12568,7 +12568,8 @@
   // instructions match the semantics of the common C idiom x<y?x:y but not
   // x<=y?x:y, because of how they handle negative zero (which can be
   // ignored in unsafe-math mode).
-  if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
+  if (Subtarget->hasXMM() &&
+      Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() &&
       VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
     ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();