[llvm-commits] [llvm] r140181 - in /llvm/trunk: lib/Target/ARM/ARM.td test/CodeGen/ARM/mulhi.ll

[Evan Cheng]

Author: evancheng
Date: Tue Sep 20 16:38:18 2011
New Revision: 140181

URL: http://llvm.org/viewvc/llvm-project?rev=140181&view=rev
Log:
Fix a bug introduced during refactoring a couple of months ago. Cortex-M3 does not support Thumb2 dsp instructions. rdar://10152911.

Modified:
    llvm/trunk/lib/Target/ARM/ARM.td
    llvm/trunk/test/CodeGen/ARM/mulhi.ll

Modified: llvm/trunk/lib/Target/ARM/ARM.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=140181&r1=140180&r2=140181&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARM.td (original)
+++ llvm/trunk/lib/Target/ARM/ARM.td Tue Sep 20 16:38:18 2011
@@ -108,7 +108,7 @@
                                    [HasV5TEOps]>;
 def HasV6T2Ops  : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
                                    "Support ARM v6t2 instructions",
-                                   [HasV6Ops, FeatureThumb2, FeatureDSPThumb2]>;
+                                   [HasV6Ops, FeatureThumb2]>;
 def HasV7Ops    : SubtargetFeature<"v7", "HasV7Ops", "true",
                                    "Support ARM v7 instructions",
                                    [HasV6T2Ops]>;
@@ -188,9 +188,11 @@
                                                        FeatureDB]>;
 
 // V6T2 Processors.
-def : Processor<"arm1156t2-s",      ARMV6Itineraries, [HasV6T2Ops]>;
+def : Processor<"arm1156t2-s",      ARMV6Itineraries, [HasV6T2Ops,
+                                                       FeatureDSPThumb2]>;
 def : Processor<"arm1156t2f-s",     ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2,
-                                                       FeatureHasSlowFPVMLx]>;
+                                                       FeatureHasSlowFPVMLx,
+                                                       FeatureDSPThumb2]>;
 
 // V7a Processors.
 def : Processor<"cortex-a8",        CortexA8Itineraries,

Modified: llvm/trunk/test/CodeGen/ARM/mulhi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/mulhi.ll?rev=140181&r1=140180&r2=140181&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/mulhi.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/mulhi.ll Tue Sep 20 16:38:18 2011
@@ -1,9 +1,16 @@
-; RUN: llc < %s -march=arm -mattr=+v6
-; RUN: llc < %s -march=arm -mattr=+v6 | \
-; RUN:   grep smmul | count 1
-; RUN: llc < %s -march=arm | grep umull | count 1
+; RUN: llc < %s -march=arm -mattr=+v6 | FileCheck %s -check-prefix=V6
+; RUN: llc < %s -march=arm | FileCheck %s -check-prefix=V4
+; RUN: llc < %s -march=thumb -mcpu=cortex-m3 | FileCheck %s -check-prefix=M3
 
-define i32 @smulhi(i32 %x, i32 %y) {
+define i32 @smulhi(i32 %x, i32 %y) nounwind {
+; V6: smulhi:
+; V6: smmul
+
+; V4: smulhi:
+; V4: smull
+
+; M3: smulhi:
+; M3: smull
         %tmp = sext i32 %x to i64               ; <i64> [#uses=1]
         %tmp1 = sext i32 %y to i64              ; <i64> [#uses=1]
         %tmp2 = mul i64 %tmp1, %tmp             ; <i64> [#uses=1]
@@ -12,7 +19,15 @@
         ret i32 %tmp3.upgrd.1
 }
 
-define i32 @umulhi(i32 %x, i32 %y) {
+define i32 @umulhi(i32 %x, i32 %y) nounwind {
+; V6: umulhi:
+; V6: umull
+
+; V4: umulhi:
+; V4: umull
+
+; M3: umulhi:
+; M3: umull
         %tmp = zext i32 %x to i64               ; <i64> [#uses=1]
         %tmp1 = zext i32 %y to i64              ; <i64> [#uses=1]
         %tmp2 = mul i64 %tmp1, %tmp             ; <i64> [#uses=1]
@@ -20,3 +35,20 @@
         %tmp3.upgrd.2 = trunc i64 %tmp3 to i32          ; <i32> [#uses=1]
         ret i32 %tmp3.upgrd.2
 }
+
+; rdar://r10152911
+define i32 @t3(i32 %a) nounwind {
+; V6: t3:
+; V6: smmla
+
+; V4: t3:
+; V4: smull
+
+; M3: t3:
+; M3-NOT: smmla
+; M3: smull
+entry:
+  %tmp1 = mul nsw i32 %a, 3
+  %tmp2 = sdiv i32 %tmp1, 23
+  ret i32 %tmp2
+}