[llvm-commits] [llvm] r140088 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td test/MC/ARM/basic-thumb2-instructions.s

[Jim Grosbach]

Author: grosbach
Date: Mon Sep 19 18:13:25 2011
New Revision: 140088

URL: http://llvm.org/viewvc/llvm-project?rev=140088&view=rev
Log:
Thumb2 assembly parsing and encoding for UHASX/UHSAX.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=140088&r1=140087&r2=140088&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Sep 19 18:13:25 2011
@@ -4954,6 +4954,10 @@
 def : MnemonicAlias<"ssubaddx", "ssax">;
 // UASX == UADDSUBX
 def : MnemonicAlias<"uaddsubx", "uasx">;
+// UHASX == UHADDSUBX
+def : MnemonicAlias<"uhaddsubx", "uhasx">;
+// UHSAX == UHSUBADDX
+def : MnemonicAlias<"uhsubaddx", "uhsax">;
 
 // LDRSBT/LDRHT/LDRSHT post-index offset if optional.
 // Note that the write-back output register is a dummy operand for MC (it's

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=140088&r1=140087&r2=140088&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Mon Sep 19 18:13:25 2011
@@ -2732,3 +2732,29 @@
 @ CHECK: itt	gt                      @ encoding: [0xc4,0xbf]
 @ CHECK: uhadd16gt	r4, r8, r2      @ encoding: [0x98,0xfa,0x62,0xf4]
 @ CHECK: uhadd8gt	r4, r8, r2      @ encoding: [0x88,0xfa,0x62,0xf4]
+
+
+ at ------------------------------------------------------------------------------
+@ UHASX/UHSAX
+ at ------------------------------------------------------------------------------
+        uhasx r4, r1, r5
+        uhsax r5, r6, r6
+        itt gt
+        uhasxgt r6, r9, r8
+        uhsaxgt r7, r8, r12
+        uhaddsubx r4, r1, r5
+        uhsubaddx r5, r6, r6
+        itt gt
+        uhaddsubxgt r6, r9, r8
+        uhsubaddxgt r7, r8, r12
+
+@ CHECK: uhasx	r4, r1, r5              @ encoding: [0xa1,0xfa,0x65,0xf4]
+@ CHECK: uhsax	r5, r6, r6              @ encoding: [0xe6,0xfa,0x66,0xf5]
+@ CHECK: itt	gt                      @ encoding: [0xc4,0xbf]
+@ CHECK: uhasxgt r6, r9, r8             @ encoding: [0xa9,0xfa,0x68,0xf6]
+@ CHECK: uhsaxgt r7, r8, r12            @ encoding: [0xe8,0xfa,0x6c,0xf7]
+@ CHECK: uhasx	r4, r1, r5              @ encoding: [0xa1,0xfa,0x65,0xf4]
+@ CHECK: uhsax	r5, r6, r6              @ encoding: [0xe6,0xfa,0x66,0xf5]
+@ CHECK: itt	gt                      @ encoding: [0xc4,0xbf]
+@ CHECK: uhasxgt r6, r9, r8             @ encoding: [0xa9,0xfa,0x68,0xf6]
+@ CHECK: uhsaxgt r7, r8, r12            @ encoding: [0xe8,0xfa,0x6c,0xf7]