[llvm-commits] [llvm] r140047 - in /llvm/trunk: lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/basic-thumb2-instructions.s test/MC/ARM/diagnostics.s
Jim Grosbach
grosbach at apple.com
Mon Sep 19 13:29:34 PDT 2011
Author: grosbach
Date: Mon Sep 19 15:29:33 2011
New Revision: 140047
URL: http://llvm.org/viewvc/llvm-project?rev=140047&view=rev
Log:
Thumb2 assembly parsing and encoding for SXTB/SXTB16/SXTH.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
llvm/trunk/test/MC/ARM/diagnostics.s
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=140047&r1=140046&r2=140047&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Mon Sep 19 15:29:33 2011
@@ -1785,8 +1785,6 @@
BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
def t2SXTAB16 : T2I_exta_rrot_np<0b010, "sxtab16">;
-// TODO: SXT(A){B|H}16
-
// Zero extenders
let AddedComplexity = 16 in {
@@ -3931,3 +3929,17 @@
(t2SXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
def : t2InstAlias<"sxtab16${p} $Rd, $Rn, $Rm",
(t2SXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>;
+def : t2InstAlias<"sxtb${p} $Rd, $Rm",
+ (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
+def : t2InstAlias<"sxtb16${p} $Rd, $Rm",
+ (t2SXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
+def : t2InstAlias<"sxth${p} $Rd, $Rm",
+ (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>;
+
+// Extend instruction w/o the ".w" optional width specifier.
+def : t2InstAlias<"sxtb${p} $Rd, $Rm$rot",
+ (t2SXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
+def : t2InstAlias<"sxtb16${p} $Rd, $Rm$rot",
+ (t2SXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
+def : t2InstAlias<"sxth${p} $Rd, $Rm$rot",
+ (t2SXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>;
Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=140047&r1=140046&r2=140047&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Sep 19 15:29:33 2011
@@ -2254,15 +2254,11 @@
parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
const AsmToken &Tok = Parser.getTok();
SMLoc S = Tok.getLoc();
- if (Tok.isNot(AsmToken::Identifier)) {
- Error(S, "rotate operator 'ror' expected");
- return MatchOperand_ParseFail;
- }
+ if (Tok.isNot(AsmToken::Identifier))
+ return MatchOperand_NoMatch;
StringRef ShiftName = Tok.getString();
- if (ShiftName != "ror" && ShiftName != "ROR") {
- Error(S, "rotate operator 'ror' expected");
- return MatchOperand_ParseFail;
- }
+ if (ShiftName != "ror" && ShiftName != "ROR")
+ return MatchOperand_NoMatch;
Parser.Lex(); // Eat the operator.
// A '#' and a rotate amount.
@@ -3867,6 +3863,28 @@
}
break;
}
+ case ARM::t2SXTH:
+ case ARM::t2SXTB: {
+ // If we can use the 16-bit encoding and the user didn't explicitly
+ // request the 32-bit variant, transform it here.
+ if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
+ isARMLowRegister(Inst.getOperand(1).getReg()) &&
+ Inst.getOperand(2).getImm() == 0 &&
+ (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
+ static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
+ unsigned NewOpc = (Inst.getOpcode() == ARM::t2SXTH) ?
+ ARM::tSXTH : ARM::tSXTB;
+ // The operands aren't the same for thumb1 (no rotate operand).
+ MCInst TmpInst;
+ TmpInst.setOpcode(NewOpc);
+ TmpInst.addOperand(Inst.getOperand(0));
+ TmpInst.addOperand(Inst.getOperand(1));
+ TmpInst.addOperand(Inst.getOperand(3));
+ TmpInst.addOperand(Inst.getOperand(4));
+ Inst = TmpInst;
+ }
+ break;
+ }
case ARM::t2IT: {
// The mask bits for all but the first condition are represented as
// the low bit of the condition code value implies 't'. We currently
Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=140047&r1=140046&r2=140047&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Mon Sep 19 15:29:33 2011
@@ -2504,3 +2504,111 @@
@ CHECK: ite hi @ encoding: [0x8c,0xbf]
@ CHECK: sxtahhi r6, r1, r6 @ encoding: [0x01,0xfa,0x86,0xf6]
@ CHECK: sxtahls r2, r2, r4, ror #16 @ encoding: [0x02,0xfa,0xa4,0xf2]
+
+
+ at ------------------------------------------------------------------------------
+@ SXTB
+ at ------------------------------------------------------------------------------
+ sxtb r5, r6, ror #0
+ sxtb r6, r9, ror #8
+ sxtb r8, r3, ror #24
+ ite ge
+ sxtbge r2, r4
+ sxtblt r5, r1, ror #16
+
+@ CHECK: sxtb r5, r6 @ encoding: [0x75,0xb2]
+@ CHECK: sxtb.w r6, r9, ror #8 @ encoding: [0x4f,0xfa,0x99,0xf6]
+@ CHECK: sxtb.w r8, r3, ror #24 @ encoding: [0x4f,0xfa,0xb3,0xf8]
+@ CHECK: ite ge @ encoding: [0xac,0xbf]
+@ CHECK: sxtbge r2, r4 @ encoding: [0x62,0xb2]
+@ CHECK: sxtblt.w r5, r1, ror #16 @ encoding: [0x4f,0xfa,0xa1,0xf5]
+
+
+ at ------------------------------------------------------------------------------
+@ SXTB16
+ at ------------------------------------------------------------------------------
+ sxtb16 r1, r4
+ sxtb16 r6, r7, ror #0
+ sxtb16 r3, r1, ror #16
+ ite cs
+ sxtb16cs r3, r5, ror #8
+ sxtb16lo r2, r3, ror #24
+
+@ CHECK: sxtb16 r1, r4 @ encoding: [0x2f,0xfa,0x84,0xf1]
+@ CHECK: sxtb16 r6, r7 @ encoding: [0x2f,0xfa,0x87,0xf6]
+@ CHECK: sxtb16 r3, r1, ror #16 @ encoding: [0x2f,0xfa,0xa1,0xf3]
+@ CHECK: ite hs @ encoding: [0x2c,0xbf]
+@ CHECK: sxtb16hs r3, r5, ror #8 @ encoding: [0x2f,0xfa,0x95,0xf3]
+@ CHECK: sxtb16lo r2, r3, ror #24 @ encoding: [0x2f,0xfa,0xb3,0xf2]
+
+
+ at ------------------------------------------------------------------------------
+@ SXTH
+ at ------------------------------------------------------------------------------
+ sxth r1, r6, ror #0
+ sxth r3, r8, ror #8
+ sxth r9, r3, ror #24
+ itt ne
+ sxthne r3, r9
+ sxthne r2, r2, ror #16
+
+@ CHECK: sxth r1, r6 @ encoding: [0x31,0xb2]
+@ CHECK: sxth.w r3, r8, ror #8 @ encoding: [0x0f,0xfa,0x98,0xf3]
+@ CHECK: sxth.w r9, r3, ror #24 @ encoding: [0x0f,0xfa,0xb3,0xf9]
+@ CHECK: itt ne @ encoding: [0x1c,0xbf]
+@ CHECK: sxthne.w r3, r9 @ encoding: [0x0f,0xfa,0x89,0xf3]
+@ CHECK: sxthne.w r2, r2, ror #16 @ encoding: [0x0f,0xfa,0xa2,0xf2]
+
+
+ at ------------------------------------------------------------------------------
+@ SXTB
+ at ------------------------------------------------------------------------------
+ sxtb r5, r6, ror #0
+ sxtb.w r6, r9, ror #8
+ sxtb r8, r3, ror #24
+ ite ge
+ sxtbge r2, r4
+ sxtblt r5, r1, ror #16
+
+@ CHECK: sxtb r5, r6 @ encoding: [0x75,0xb2]
+@ CHECK: sxtb.w r6, r9, ror #8 @ encoding: [0x4f,0xfa,0x99,0xf6]
+@ CHECK: sxtb.w r8, r3, ror #24 @ encoding: [0x4f,0xfa,0xb3,0xf8]
+@ CHECK: ite ge @ encoding: [0xac,0xbf]
+@ CHECK: sxtbge r2, r4 @ encoding: [0x62,0xb2]
+@ CHECK: sxtblt.w r5, r1, ror #16 @ encoding: [0x4f,0xfa,0xa1,0xf5]
+
+
+ at ------------------------------------------------------------------------------
+@ SXTB16
+ at ------------------------------------------------------------------------------
+ sxtb16 r1, r4
+ sxtb16 r6, r7, ror #0
+ sxtb16 r3, r1, ror #16
+ ite cs
+ sxtb16cs r3, r5, ror #8
+ sxtb16lo r2, r3, ror #24
+
+@ CHECK: sxtb16 r1, r4 @ encoding: [0x2f,0xfa,0x84,0xf1]
+@ CHECK: sxtb16 r6, r7 @ encoding: [0x2f,0xfa,0x87,0xf6]
+@ CHECK: sxtb16 r3, r1, ror #16 @ encoding: [0x2f,0xfa,0xa1,0xf3]
+@ CHECK: ite hs @ encoding: [0x2c,0xbf]
+@ CHECK: sxtb16hs r3, r5, ror #8 @ encoding: [0x2f,0xfa,0x95,0xf3]
+@ CHECK: sxtb16lo r2, r3, ror #24 @ encoding: [0x2f,0xfa,0xb3,0xf2]
+
+
+ at ------------------------------------------------------------------------------
+@ SXTH
+ at ------------------------------------------------------------------------------
+ sxth r1, r6, ror #0
+ sxth.w r3, r8, ror #8
+ sxth r9, r3, ror #24
+ itt ne
+ sxthne r3, r9
+ sxthne r2, r2, ror #16
+
+@ CHECK: sxth r1, r6 @ encoding: [0x31,0xb2]
+@ CHECK: sxth.w r3, r8, ror #8 @ encoding: [0x0f,0xfa,0x98,0xf3]
+@ CHECK: sxth.w r9, r3, ror #24 @ encoding: [0x0f,0xfa,0xb3,0xf9]
+@ CHECK: itt ne @ encoding: [0x1c,0xbf]
+@ CHECK: sxthne.w r3, r9 @ encoding: [0x0f,0xfa,0x89,0xf3]
+@ CHECK: sxthne.w r2, r2, ror #16 @ encoding: [0x0f,0xfa,0xa2,0xf2]
Modified: llvm/trunk/test/MC/ARM/diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/diagnostics.s?rev=140047&r1=140046&r2=140047&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/diagnostics.s (original)
+++ llvm/trunk/test/MC/ARM/diagnostics.s Mon Sep 19 15:29:33 2011
@@ -248,7 +248,7 @@
sxtah r9, r3, r3, ror #-8
sxtb16ge r2, r3, lsr #24
-@ CHECK-ERRORS: error: rotate operator 'ror' expected
+@ CHECK-ERRORS: error: invalid operand for instruction
@ CHECK-ERRORS: sxtb r8, r3, #8
@ CHECK-ERRORS: ^
@ CHECK-ERRORS: error: '#' expected
@@ -269,7 +269,7 @@
@ CHECK-ERRORS: error: 'ror' rotate amount must be 8, 16, or 24
@ CHECK-ERRORS: sxtah r9, r3, r3, ror #-8
@ CHECK-ERRORS: ^
-@ CHECK-ERRORS: error: rotate operator 'ror' expected
+@ CHECK-ERRORS: error: invalid operand for instruction
@ CHECK-ERRORS: sxtb16ge r2, r3, lsr #24
@ CHECK-ERRORS: ^
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