[llvm-commits] [llvm] r140003 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

[Nadav Rotem]

Author: nadav
Date: Sun Sep 18 14:00:23 2011
New Revision: 140003

URL: http://llvm.org/viewvc/llvm-project?rev=140003&view=rev
Log:
Fix typos in my prev commit, found by Tobi.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=140003&r1=140002&r2=140003&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sun Sep 18 14:00:23 2011
@@ -13445,7 +13445,7 @@
 
   ISD::LoadExtType Ext = Ld->getExtensionType();
 
-  // If yhis is a vector EXT Load then attempt to optimize it using a
+  // If this is a vector EXT Load then attempt to optimize it using a
   // shuffle. We need SSE4 for the shuffles.
   // TODO: It is possible to support ZExt by zeroing the undef values
   // during the shuffle phase or after the shuffle.
@@ -13457,7 +13457,7 @@
     unsigned RegSz = RegVT.getSizeInBits();
     unsigned MemSz = MemVT.getSizeInBits();
     assert(RegSz > MemSz && "Register size must be greater than the mem size");
-    // All sized must be a power of two
+    // All sizes must be a power of two
     if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue();
 
     // Attempt to load the original value using a single load op.