[llvm-commits] [llvm] r139929 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td test/MC/ARM/basic-thumb2-instructions.s

[Jim Grosbach]

Author: grosbach
Date: Fri Sep 16 13:37:10 2011
New Revision: 139929

URL: http://llvm.org/viewvc/llvm-project?rev=139929&view=rev
Log:
Thumb2 assembly parsing and encoding for SSAX.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=139929&r1=139928&r2=139929&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Fri Sep 16 13:37:10 2011
@@ -4950,6 +4950,8 @@
 def : MnemonicAlias<"shaddsubx", "shasx">;
 // SHSAX == SHSUBADDX
 def : MnemonicAlias<"shsubaddx", "shsax">;
+// SSAX == SSUBADDX
+def : MnemonicAlias<"ssubaddx", "ssax">;
 
 // LDRSBT/LDRHT/LDRSHT post-index offset if optional.
 // Note that the write-back output register is a dummy operand for MC (it's

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=139929&r1=139928&r2=139929&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Fri Sep 16 13:37:10 2011
@@ -2075,6 +2075,24 @@
 
 
 @------------------------------------------------------------------------------
+@ SSAX
+ at ------------------------------------------------------------------------------
+        ssubaddx r2, r3, r4
+        it lt
+        ssubaddxlt r2, r3, r4
+        ssax r2, r3, r4
+        it lt
+        ssaxlt r2, r3, r4
+
+@ CHECK: ssax	r2, r3, r4              @ encoding: [0xe3,0xfa,0x04,0xf2]
+@ CHECK: it	lt                      @ encoding: [0xb8,0xbf]
+@ CHECK: ssaxlt	r2, r3, r4              @ encoding: [0xe3,0xfa,0x04,0xf2]
+@ CHECK: ssax	r2, r3, r4              @ encoding: [0xe3,0xfa,0x04,0xf2]
+@ CHECK: it	lt                      @ encoding: [0xb8,0xbf]
+@ CHECK: ssaxlt	r2, r3, r4              @ encoding: [0xe3,0xfa,0x04,0xf2]
+
+
+ at ------------------------------------------------------------------------------
 @ SUB (register)
 @------------------------------------------------------------------------------
         sub.w r5, r2, r12, rrx