[llvm-commits] [llvm] r139870 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td test/MC/ARM/basic-thumb2-instructions.s

[Jim Grosbach]

Author: grosbach
Date: Thu Sep 15 17:34:29 2011
New Revision: 139870

URL: http://llvm.org/viewvc/llvm-project?rev=139870&view=rev
Log:
Thumb2 assembly parsing and encoding for SHASX/SHSAX.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=139870&r1=139869&r2=139870&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Sep 15 17:34:29 2011
@@ -4946,6 +4946,10 @@
 def : MnemonicAlias<"qsubaddx", "qsax">;
 // SASX == SADDSUBX
 def : MnemonicAlias<"saddsubx", "sasx">;
+// SHASX == SHADDSUBX
+def : MnemonicAlias<"shaddsubx", "shasx">;
+// SHSAX == SHSUBADDX
+def : MnemonicAlias<"shsubaddx", "shsax">;
 
 // LDRSBT/LDRHT/LDRSHT post-index offset if optional.
 // Note that the write-back output register is a dummy operand for MC (it's

Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=139870&r1=139869&r2=139870&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Thu Sep 15 17:34:29 2011
@@ -1679,6 +1679,42 @@
 
 
 @------------------------------------------------------------------------------
+@ SHASX
+ at ------------------------------------------------------------------------------
+        shasx r4, r8, r2
+        it gt
+        shasxgt r4, r8, r2
+        shaddsubx r4, r8, r2
+        it gt
+        shaddsubxgt r4, r8, r2
+
+@ CHECK: shasx	r4, r8, r2              @ encoding: [0xa8,0xfa,0x22,0xf4]
+@ CHECK: it	gt                      @ encoding: [0xc8,0xbf]
+@ CHECK: shasxgt r4, r8, r2             @ encoding: [0xa8,0xfa,0x22,0xf4]
+@ CHECK: shasx	r4, r8, r2              @ encoding: [0xa8,0xfa,0x22,0xf4]
+@ CHECK: it	gt                      @ encoding: [0xc8,0xbf]
+@ CHECK: shasxgt r4, r8, r2             @ encoding: [0xa8,0xfa,0x22,0xf4]
+
+
+ at ------------------------------------------------------------------------------
+@ SHASX
+ at ------------------------------------------------------------------------------
+        shsax r4, r8, r2
+        it gt
+        shsaxgt r4, r8, r2
+        shsubaddx r4, r8, r2
+        it gt
+        shsubaddxgt r4, r8, r2
+
+@ CHECK: shsax	r4, r8, r2              @ encoding: [0xe8,0xfa,0x22,0xf4]
+@ CHECK: it	gt                      @ encoding: [0xc8,0xbf]
+@ CHECK: shsaxgt r4, r8, r2             @ encoding: [0xe8,0xfa,0x22,0xf4]
+@ CHECK: shsax	r4, r8, r2              @ encoding: [0xe8,0xfa,0x22,0xf4]
+@ CHECK: it	gt                      @ encoding: [0xc8,0xbf]
+@ CHECK: shsaxgt r4, r8, r2             @ encoding: [0xe8,0xfa,0x22,0xf4]
+
+
+ at ------------------------------------------------------------------------------
 @ SUB (register)
 @------------------------------------------------------------------------------
         sub.w r5, r2, r12, rrx