[llvm-commits] [llvm] r139634 - in /llvm/trunk: lib/Target/Mips/MipsInstrInfo.td test/CodeGen/Mips/mipslopat.ll

[Akira Hatanaka]

Author: ahatanak
Date: Tue Sep 13 15:13:58 2011
New Revision: 139634

URL: http://llvm.org/viewvc/llvm-project?rev=139634&view=rev
Log:
Add pattern used to match MipsLo, which is needed when the instruction selector
tries to match a dead MipsLo node (explanation in the link below).

http://article.gmane.org/gmane.comp.compilers.llvm.devel/42757/match=dagcombiner+dead


Added:
    llvm/trunk/test/CodeGen/Mips/mipslopat.ll
Modified:
    llvm/trunk/lib/Target/Mips/MipsInstrInfo.td

Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=139634&r1=139633&r2=139634&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Tue Sep 13 15:13:58 2011
@@ -734,16 +734,20 @@
 // hi/lo relocs
 def : Pat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
 def : Pat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
+def : Pat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
+def : Pat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
 def : Pat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
           (ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
 def : Pat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)),
           (ADDiu CPURegs:$hi, tblockaddress:$lo)>;
 
 def : Pat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
+def : Pat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
 def : Pat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)),
           (ADDiu CPURegs:$hi, tjumptable:$lo)>;
 
 def : Pat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
+def : Pat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
 def : Pat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)),
           (ADDiu CPURegs:$hi, tconstpool:$lo)>;
 
@@ -759,6 +763,7 @@
 
 // tprel hi/lo
 def : Pat<(MipsTprelHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
+def : Pat<(MipsTprelLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
 def : Pat<(add CPURegs:$hi, (MipsTprelLo tglobaltlsaddr:$lo)),
           (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>;
 

Added: llvm/trunk/test/CodeGen/Mips/mipslopat.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mipslopat.ll?rev=139634&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/mipslopat.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/mipslopat.ll Tue Sep 13 15:13:58 2011
@@ -0,0 +1,19 @@
+; This test does not check the machine code output.   
+; RUN: llc -march=mips < %s 
+
+ at stat_vol_ptr_int = internal global i32* null, align 4
+ at stat_ptr_vol_int = internal global i32* null, align 4
+
+define void @simple_vol_file() nounwind {
+entry:
+  %tmp = volatile load i32** @stat_vol_ptr_int, align 4
+  %0 = bitcast i32* %tmp to i8*
+  call void @llvm.prefetch(i8* %0, i32 0, i32 0, i32 1)
+  %tmp1 = load i32** @stat_ptr_vol_int, align 4
+  %1 = bitcast i32* %tmp1 to i8*
+  call void @llvm.prefetch(i8* %1, i32 0, i32 0, i32 1)
+  ret void
+}
+
+declare void @llvm.prefetch(i8* nocapture, i32, i32, i32) nounwind
+