[llvm-commits] [llvm] r139405 - in /llvm/trunk: lib/Target/Mips/ test/CodeGen/Mips/
Bruno Cardoso Lopes
bruno.cardoso at gmail.com
Fri Sep 9 14:05:11 PDT 2011
yay! :D
On Fri, Sep 9, 2011 at 1:45 PM, Akira Hatanaka <ahatanak at gmail.com> wrote:
> Author: ahatanak
> Date: Fri Sep 9 15:45:50 2011
> New Revision: 139405
>
> URL: http://llvm.org/viewvc/llvm-project?rev=139405&view=rev
> Log:
> Drop support for Mips1 and Mips2.
>
> Removed:
> llvm/trunk/test/CodeGen/Mips/mips1f64ldst.ll
> Modified:
> llvm/trunk/lib/Target/Mips/Mips.td
> llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp
> llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp
> llvm/trunk/lib/Target/Mips/MipsInstrFPU.td
> llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
> llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp
> llvm/trunk/lib/Target/Mips/MipsMCInstLower.h
> llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp
> llvm/trunk/lib/Target/Mips/MipsSubtarget.h
> llvm/trunk/test/CodeGen/Mips/2010-07-20-Select.ll
> llvm/trunk/test/CodeGen/Mips/atomic.ll
> llvm/trunk/test/CodeGen/Mips/fpcmp.ll
> llvm/trunk/test/CodeGen/Mips/frame-address.ll
> llvm/trunk/test/CodeGen/Mips/o32_cc_vararg.ll
> llvm/trunk/test/CodeGen/Mips/select.ll
> llvm/trunk/test/CodeGen/Mips/tls.ll
>
> Modified: llvm/trunk/lib/Target/Mips/Mips.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips.td?rev=139405&r1=139404&r2=139405&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/Mips.td (original)
> +++ llvm/trunk/lib/Target/Mips/Mips.td Fri Sep 9 15:45:50 2011
> @@ -54,10 +54,6 @@
> "Enable 'byte/half swap' instructions.">;
> def FeatureBitCount : SubtargetFeature<"bitcount", "HasBitCount", "true",
> "Enable 'count leading bits' instructions.">;
> -def FeatureMips1 : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1",
> - "Mips1 ISA Support">;
> -def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
> - "Mips2 ISA Support">;
> def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
> "Mips32 ISA Support",
> [FeatureCondMov, FeatureBitCount]>;
> @@ -72,13 +68,6 @@
> class Proc<string Name, list<SubtargetFeature> Features>
> : Processor<Name, MipsGenericItineraries, Features>;
>
> -def : Proc<"mips1", [FeatureMips1]>;
> -def : Proc<"r2000", [FeatureMips1]>;
> -def : Proc<"r3000", [FeatureMips1]>;
> -
> -def : Proc<"mips2", [FeatureMips2]>;
> -def : Proc<"r6000", [FeatureMips2]>;
> -
> def : Proc<"mips32r1", [FeatureMips32]>;
> def : Proc<"4ke", [FeatureMips32r2]>;
>
>
> Modified: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp?rev=139405&r1=139404&r2=139405&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp Fri Sep 9 15:45:50 2011
> @@ -36,7 +36,6 @@
> #include "llvm/Target/TargetLoweringObjectFile.h"
> #include "llvm/Target/TargetOptions.h"
> #include "llvm/ADT/SmallString.h"
> -#include "llvm/ADT/SmallVector.h"
> #include "llvm/ADT/StringExtras.h"
> #include "llvm/ADT/Twine.h"
> #include "llvm/Support/TargetRegistry.h"
> @@ -56,23 +55,6 @@
>
> MipsMCInstLower MCInstLowering(Mang, *MF, *this);
> unsigned Opc = MI->getOpcode();
> -
> - // If target is Mips1, expand double precision load/store to two single
> - // precision loads/stores (and delay slot if MI is a load).
> - if (Subtarget->isMips1() && (Opc == Mips::LDC1 || Opc == Mips::SDC1)) {
> - SmallVector<MCInst, 4> MCInsts;
> - const unsigned* SubReg =
> - TM.getRegisterInfo()->getSubRegisters(MI->getOperand(0).getReg());
> - MCInstLowering.LowerMips1F64LoadStore(MI, Opc, MCInsts,
> - Subtarget->isLittle(), SubReg);
> -
> - for (SmallVector<MCInst, 4>::iterator I = MCInsts.begin();
> - I != MCInsts.end(); ++I)
> - OutStreamer.EmitInstruction(*I);
> -
> - return;
> - }
> -
> MCInst TmpInst0;
> MCInstLowering.Lower(MI, TmpInst0);
>
>
> Modified: llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp?rev=139405&r1=139404&r2=139405&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp Fri Sep 9 15:45:50 2011
> @@ -60,9 +60,7 @@
> bool Changed = false;
> for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I) {
> const MCInstrDesc& MCid = I->getDesc();
> - if (MCid.hasDelaySlot() &&
> - (TM.getSubtarget<MipsSubtarget>().isMips1() ||
> - MCid.isCall() || MCid.isBranch() || MCid.isReturn())) {
> + if (MCid.hasDelaySlot()) {
> MachineBasicBlock::iterator J = I;
> ++J;
> BuildMI(MBB, J, I->getDebugLoc(), TII->get(Mips::NOP));
>
> Modified: llvm/trunk/lib/Target/Mips/MipsInstrFPU.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFPU.td?rev=139405&r1=139404&r2=139405&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsInstrFPU.td (original)
> +++ llvm/trunk/lib/Target/Mips/MipsInstrFPU.td Fri Sep 9 15:45:50 2011
> @@ -58,7 +58,6 @@
> def In32BitMode : Predicate<"!Subtarget.isFP64bit()">;
> def IsSingleFloat : Predicate<"Subtarget.isSingleFloat()">;
> def IsNotSingleFloat : Predicate<"!Subtarget.isSingleFloat()">;
> -def IsNotMipsI : Predicate<"!Subtarget.isMips1()">;
>
> //===----------------------------------------------------------------------===//
> // Instruction Class Templates
> @@ -254,7 +253,7 @@
> def MIPS_FCOND_NGT : PatLeaf<(i32 15)>;
>
> /// Floating Point Compare
> -let hasDelaySlot = 1, Defs=[FCR31] in {
> +let Defs=[FCR31] in {
> def FCMP_S32 : FCC<0x0, (outs), (ins FGR32:$fs, FGR32:$ft, condcode:$cc),
> "c.$cc.s\t$fs, $ft",
> [(MipsFPCmp FGR32:$fs, FGR32:$ft, imm:$cc)]>;
>
> Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=139405&r1=139404&r2=139405&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Fri Sep 9 15:45:50 2011
> @@ -273,7 +273,7 @@
> [], IIAlu>;
>
> // Memory Load/Store
> -let canFoldAsLoad = 1, hasDelaySlot = 1 in
> +let canFoldAsLoad = 1 in
> class LoadM<bits<6> op, string instr_asm, PatFrag OpNode>:
> FI<op, (outs CPURegs:$dst), (ins mem:$addr),
> !strconcat(instr_asm, "\t$dst, $addr"),
> @@ -571,7 +571,7 @@
> }
>
> /// Load-linked, Store-conditional
> -let mayLoad = 1, hasDelaySlot = 1 in
> +let mayLoad = 1 in
> def LL : FI<0x30, (outs CPURegs:$dst), (ins mem:$addr),
> "ll\t$dst, $addr", [], IILoad>;
> let mayStore = 1, Constraints = "$src = $dst" in
>
> Modified: llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp?rev=139405&r1=139404&r2=139405&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp Fri Sep 9 15:45:50 2011
> @@ -83,50 +83,6 @@
> Ctx));
> }
>
> -// If target is Mips1, expand double precision load/store to two single
> -// precision loads/stores.
> -//
> -// ldc1 $f0, lo($CPI0_0)($5) gets expanded to the following two instructions:
> -// (little endian)
> -// lwc1 $f0, lo($CPI0_0)($5) and
> -// lwc1 $f1, lo($CPI0_0+4)($5)
> -// (big endian)
> -// lwc1 $f1, lo($CPI0_0)($5) and
> -// lwc1 $f0, lo($CPI0_0+4)($5)
> -void MipsMCInstLower::LowerMips1F64LoadStore(const MachineInstr *MI,
> - unsigned Opc,
> - SmallVector<MCInst, 4>& MCInsts,
> - bool isLittle,
> - const unsigned *SubReg) const {
> - MCInst InstLo, InstHi, DelaySlot;
> - unsigned SingleOpc = (Opc == Mips::LDC1 ? Mips::LWC1 : Mips::SWC1);
> - unsigned RegLo = isLittle ? *SubReg : *(SubReg + 1);
> - unsigned RegHi = isLittle ? *(SubReg + 1) : *SubReg;
> - const MachineOperand &MO1 = MI->getOperand(1);
> - const MachineOperand &MO2 = MI->getOperand(2);
> -
> - InstLo.setOpcode(SingleOpc);
> - InstLo.addOperand(MCOperand::CreateReg(RegLo));
> - InstLo.addOperand(LowerOperand(MO1));
> - InstLo.addOperand(LowerOperand(MO2));
> - MCInsts.push_back(InstLo);
> -
> - InstHi.setOpcode(SingleOpc);
> - InstHi.addOperand(MCOperand::CreateReg(RegHi));
> - InstHi.addOperand(LowerOperand(MO1));
> - if (MO2.isImm())// The offset of addr operand is an immediate: e.g. 0($sp)
> - InstHi.addOperand(MCOperand::CreateImm(MO2.getImm() + 4));
> - else// Otherwise, the offset must be a symbol: e.g. lo($CPI0_0)($5)
> - InstHi.addOperand(LowerSymbolOperand(MO2, MO2.getType(), 4));
> - MCInsts.push_back(InstHi);
> -
> - // Need to insert a NOP in LWC1's delay slot.
> - if (SingleOpc == Mips::LWC1) {
> - DelaySlot.setOpcode(Mips::NOP);
> - MCInsts.push_back(DelaySlot);
> - }
> -}
> -
> MCOperand MipsMCInstLower::LowerOperand(const MachineOperand& MO) const {
> MachineOperandType MOTy = MO.getType();
>
>
> Modified: llvm/trunk/lib/Target/Mips/MipsMCInstLower.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMCInstLower.h?rev=139405&r1=139404&r2=139405&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsMCInstLower.h (original)
> +++ llvm/trunk/lib/Target/Mips/MipsMCInstLower.h Fri Sep 9 15:45:50 2011
> @@ -9,7 +9,6 @@
>
> #ifndef MIPSMCINSTLOWER_H
> #define MIPSMCINSTLOWER_H
> -#include "llvm/ADT/SmallVector.h"
> #include "llvm/CodeGen/MachineOperand.h"
> #include "llvm/Support/Compiler.h"
>
> @@ -35,9 +34,6 @@
> MipsMCInstLower(Mangler *mang, const MachineFunction &MF,
> MipsAsmPrinter &asmprinter);
> void Lower(const MachineInstr *MI, MCInst &OutMI) const;
> - void LowerMips1F64LoadStore(const MachineInstr *MI, unsigned Opc,
> - SmallVector<MCInst, 4>& MCInsts,
> - bool isLittle, const unsigned *SubReg) const;
> private:
> MCOperand LowerSymbolOperand(const MachineOperand &MO,
> MachineOperandType MOTy, unsigned Offset) const;
>
> Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp?rev=139405&r1=139404&r2=139405&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp Fri Sep 9 15:45:50 2011
> @@ -24,7 +24,7 @@
> MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
> const std::string &FS, bool little) :
> MipsGenSubtargetInfo(TT, CPU, FS),
> - MipsArchVersion(Mips1), MipsABI(O32), IsLittle(little), IsSingleFloat(false),
> + MipsArchVersion(Mips32), MipsABI(O32), IsLittle(little), IsSingleFloat(false),
> IsFP64bit(false), IsGP64bit(false), HasVFPU(false), IsLinux(true),
> HasSEInReg(false), HasCondMov(false), HasMulDivAdd(false), HasMinMax(false),
> HasSwap(false), HasBitCount(false)
>
> Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.h?rev=139405&r1=139404&r2=139405&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsSubtarget.h (original)
> +++ llvm/trunk/lib/Target/Mips/MipsSubtarget.h Fri Sep 9 15:45:50 2011
> @@ -34,7 +34,7 @@
> protected:
>
> enum MipsArchEnum {
> - Mips1, Mips2, Mips3, Mips4, Mips32, Mips32r2
> + Mips32, Mips32r2
> };
>
> // Mips architecture version
> @@ -102,7 +102,6 @@
> /// subtarget options. Definition of function is auto generated by tblgen.
> void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
>
> - bool isMips1() const { return MipsArchVersion == Mips1; }
> bool isMips32() const { return MipsArchVersion >= Mips32; }
> bool isMips32r2() const { return MipsArchVersion == Mips32r2; }
>
>
> Modified: llvm/trunk/test/CodeGen/Mips/2010-07-20-Select.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2010-07-20-Select.ll?rev=139405&r1=139404&r2=139405&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/2010-07-20-Select.ll (original)
> +++ llvm/trunk/test/CodeGen/Mips/2010-07-20-Select.ll Fri Sep 9 15:45:50 2011
> @@ -1,7 +1,10 @@
> -; RUN: llc < %s -march=mips -relocation-model=static -mcpu=mips1 | FileCheck %s
> -; RUN: llc < %s -march=mips -relocation-model=static -regalloc=basic -mcpu=mips1 | FileCheck %s
> +; DISABLED: llc < %s -march=mips -relocation-model=static | FileCheck %s
> +; DISABLED: llc < %s -march=mips -relocation-model=static -regalloc=basic | FileCheck %s
> +; RUN: false
> ++; XFAIL: *
> ; Fix PR7473
>
> +
> define i32 @main() nounwind readnone {
> entry:
> %a = alloca i32, align 4 ; <i32*> [#uses=2]
>
> Modified: llvm/trunk/test/CodeGen/Mips/atomic.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/atomic.ll?rev=139405&r1=139404&r2=139405&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/atomic.ll (original)
> +++ llvm/trunk/test/CodeGen/Mips/atomic.ll Fri Sep 9 15:45:50 2011
> @@ -1,4 +1,4 @@
> -; RUN: llc -march=mipsel -mcpu=mips2 < %s | FileCheck %s
> +; RUN: llc -march=mipsel < %s | FileCheck %s
>
>
> declare i32 @llvm.atomic.load.add.i32.p0i32(i32* nocapture, i32) nounwind
>
> Modified: llvm/trunk/test/CodeGen/Mips/fpcmp.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/fpcmp.ll?rev=139405&r1=139404&r2=139405&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/fpcmp.ll (original)
> +++ llvm/trunk/test/CodeGen/Mips/fpcmp.ll Fri Sep 9 15:45:50 2011
> @@ -1,5 +1,4 @@
> ; RUN: llc < %s -march=mipsel -mcpu=4ke | FileCheck %s -check-prefix=CHECK-MIPS32R2
> -; RUN: llc < %s -march=mipsel -mcpu=mips1 | FileCheck %s -check-prefix=CHECK-MIPS1
>
> @g1 = external global i32
>
> @@ -9,10 +8,6 @@
> ; CHECK-MIPS32R2: movt
> ; CHECK-MIPS32R2: c.olt.s
> ; CHECK-MIPS32R2: movt
> -; CHECK-MIPS1: c.olt.s
> -; CHECK-MIPS1: bc1t
> -; CHECK-MIPS1: c.olt.s
> -; CHECK-MIPS1: bc1t
> %cmp = fcmp olt float %f0, %f1
> %conv = zext i1 %cmp to i32
> %tmp2 = load i32* @g1, align 4
>
> Modified: llvm/trunk/test/CodeGen/Mips/frame-address.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/frame-address.ll?rev=139405&r1=139404&r2=139405&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/frame-address.ll (original)
> +++ llvm/trunk/test/CodeGen/Mips/frame-address.ll Fri Sep 9 15:45:50 2011
> @@ -1,4 +1,4 @@
> -; RUN: llc -march=mipsel -mcpu=mips2 < %s | FileCheck %s
> +; RUN: llc -march=mipsel < %s | FileCheck %s
>
> declare i8* @llvm.frameaddress(i32) nounwind readnone
>
>
> Removed: llvm/trunk/test/CodeGen/Mips/mips1f64ldst.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/mips1f64ldst.ll?rev=139404&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/mips1f64ldst.ll (original)
> +++ llvm/trunk/test/CodeGen/Mips/mips1f64ldst.ll (removed)
> @@ -1,36 +0,0 @@
> -; RUN: llc < %s -march=mipsel -mcpu=mips1 | FileCheck %s -check-prefix=CHECK-EL
> -; RUN: llc < %s -march=mips -mcpu=mips1 | FileCheck %s -check-prefix=CHECK-EB
> -
> - at g1 = common global double 0.000000e+00, align 8
> - at g2 = common global double 0.000000e+00, align 8
> -
> -define double @foo0(double %d0) nounwind {
> -entry:
> -; CHECK-EL: lw $[[R0:[0-9]+]], %got($CPI0_0)
> -; CHECK-EL: lwc1 $f[[R1:[0-9]+]], %lo($CPI0_0)($[[R0]])
> -; CHECK-EL: lwc1 $f{{[0-9]+}}, %lo($CPI0_0+4)($[[R0]])
> -; CHECK-EL: add.d $f[[R2:[0-9]+]], $f12, $f[[R1]]
> -; CHECK-EL: lw $[[R3:[0-9]+]], %got(g1)
> -; CHECK-EL: swc1 $f[[R2]], 0($[[R3]])
> -; CHECK-EL: swc1 $f{{[0-9]+}}, 4($[[R3]])
> -; CHECK-EL: lw $[[R4:[0-9]+]], %got(g2)
> -; CHECK-EL: lwc1 $f0, 0($[[R4]])
> -; CHECK-EL: lwc1 $f1, 4($[[R4]])
> -
> -; CHECK-EB: lw $[[R0:[0-9]+]], %got($CPI0_0)
> -; CHECK-EB: lwc1 $f{{[0-9]+}}, %lo($CPI0_0)($[[R0]])
> -; CHECK-EB: lwc1 $f[[R1:[0-9]+]], %lo($CPI0_0+4)($[[R0]])
> -; CHECK-EB: add.d $f[[R2:[0-9]+]], $f12, $f[[R1]]
> -; CHECK-EB: lw $[[R3:[0-9]+]], %got(g1)
> -; CHECK-EB: swc1 $f{{[0-9]+}}, 0($[[R3]])
> -; CHECK-EB: swc1 $f[[R2]], 4($[[R3]])
> -; CHECK-EB: lw $[[R4:[0-9]+]], %got(g2)
> -; CHECK-EB: lwc1 $f1, 0($[[R4]])
> -; CHECK-EB: lwc1 $f0, 4($[[R4]])
> -
> - %add = fadd double %d0, 2.000000e+00
> - store double %add, double* @g1, align 8
> - %tmp1 = load double* @g2, align 8
> - ret double %tmp1
> -}
> -
>
> Modified: llvm/trunk/test/CodeGen/Mips/o32_cc_vararg.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/o32_cc_vararg.ll?rev=139405&r1=139404&r2=139405&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/o32_cc_vararg.ll (original)
> +++ llvm/trunk/test/CodeGen/Mips/o32_cc_vararg.ll Fri Sep 9 15:45:50 2011
> @@ -1,4 +1,4 @@
> -; RUN: llc -march=mipsel -mcpu=mips2 -pre-RA-sched=source < %s | FileCheck %s
> +; RUN: llc -march=mipsel -pre-RA-sched=source < %s | FileCheck %s
>
>
> ; All test functions do the same thing - they return the first variable
>
> Modified: llvm/trunk/test/CodeGen/Mips/select.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/select.ll?rev=139405&r1=139404&r2=139405&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/select.ll (original)
> +++ llvm/trunk/test/CodeGen/Mips/select.ll Fri Sep 9 15:45:50 2011
> @@ -1,5 +1,4 @@
> ; RUN: llc < %s -march=mipsel -mcpu=4ke | FileCheck %s -check-prefix=CHECK-MIPS32R2
> -; RUN: llc < %s -march=mipsel -mcpu=mips1 | FileCheck %s -check-prefix=CHECK-MIPS1
>
> @d2 = external global double
> @d3 = external global double
> @@ -7,7 +6,6 @@
> define i32 @sel1(i32 %s, i32 %f0, i32 %f1) nounwind readnone {
> entry:
> ; CHECK-MIPS32R2: movn
> -; CHECK-MIPS1: beq
> %tobool = icmp ne i32 %s, 0
> %cond = select i1 %tobool, i32 %f1, i32 %f0
> ret i32 %cond
> @@ -16,7 +14,6 @@
> define float @sel2(i32 %s, float %f0, float %f1) nounwind readnone {
> entry:
> ; CHECK-MIPS32R2: movn.s
> -; CHECK-MIPS1: beq
> %tobool = icmp ne i32 %s, 0
> %cond = select i1 %tobool, float %f0, float %f1
> ret float %cond
> @@ -25,7 +22,6 @@
> define double @sel2_1(i32 %s, double %f0, double %f1) nounwind readnone {
> entry:
> ; CHECK-MIPS32R2: movn.d
> -; CHECK-MIPS1: bne
> %tobool = icmp ne i32 %s, 0
> %cond = select i1 %tobool, double %f0, double %f1
> ret double %cond
> @@ -35,8 +31,6 @@
> entry:
> ; CHECK-MIPS32R2: c.eq.s
> ; CHECK-MIPS32R2: movt.s
> -; CHECK-MIPS1: c.eq.s
> -; CHECK-MIPS1: bc1f
> %cmp = fcmp oeq float %f2, %f3
> %cond = select i1 %cmp, float %f0, float %f1
> ret float %cond
> @@ -46,8 +40,6 @@
> entry:
> ; CHECK-MIPS32R2: c.olt.s
> ; CHECK-MIPS32R2: movt.s
> -; CHECK-MIPS1: c.olt.s
> -; CHECK-MIPS1: bc1f
> %cmp = fcmp olt float %f2, %f3
> %cond = select i1 %cmp, float %f0, float %f1
> ret float %cond
> @@ -57,8 +49,6 @@
> entry:
> ; CHECK-MIPS32R2: c.ule.s
> ; CHECK-MIPS32R2: movf.s
> -; CHECK-MIPS1: c.ule.s
> -; CHECK-MIPS1: bc1t
> %cmp = fcmp ogt float %f2, %f3
> %cond = select i1 %cmp, float %f0, float %f1
> ret float %cond
> @@ -68,8 +58,6 @@
> entry:
> ; CHECK-MIPS32R2: c.ule.s
> ; CHECK-MIPS32R2: movf.d
> -; CHECK-MIPS1: c.ule.s
> -; CHECK-MIPS1: bc1t
> %cmp = fcmp ogt float %f2, %f3
> %cond = select i1 %cmp, double %f0, double %f1
> ret double %cond
> @@ -79,8 +67,6 @@
> entry:
> ; CHECK-MIPS32R2: c.eq.d
> ; CHECK-MIPS32R2: movt.d
> -; CHECK-MIPS1: c.eq.d
> -; CHECK-MIPS1: bc1f
> %cmp = fcmp oeq double %f2, %f3
> %cond = select i1 %cmp, double %f0, double %f1
> ret double %cond
> @@ -90,8 +76,6 @@
> entry:
> ; CHECK-MIPS32R2: c.olt.d
> ; CHECK-MIPS32R2: movt.d
> -; CHECK-MIPS1: c.olt.d
> -; CHECK-MIPS1: bc1f
> %cmp = fcmp olt double %f2, %f3
> %cond = select i1 %cmp, double %f0, double %f1
> ret double %cond
> @@ -101,8 +85,6 @@
> entry:
> ; CHECK-MIPS32R2: c.ule.d
> ; CHECK-MIPS32R2: movf.d
> -; CHECK-MIPS1: c.ule.d
> -; CHECK-MIPS1: bc1t
> %cmp = fcmp ogt double %f2, %f3
> %cond = select i1 %cmp, double %f0, double %f1
> ret double %cond
> @@ -112,8 +94,6 @@
> entry:
> ; CHECK-MIPS32R2: c.ule.d
> ; CHECK-MIPS32R2: movf.s
> -; CHECK-MIPS1: c.ule.d
> -; CHECK-MIPS1: bc1t
> %cmp = fcmp ogt double %f2, %f3
> %cond = select i1 %cmp, float %f0, float %f1
> ret float %cond
> @@ -123,8 +103,6 @@
> entry:
> ; CHECK-MIPS32R2: c.eq.s
> ; CHECK-MIPS32R2: movt
> -; CHECK-MIPS1: c.eq.s
> -; CHECK-MIPS1: bc1f
> %cmp = fcmp oeq float %f2, %f3
> %cond = select i1 %cmp, i32 %f0, i32 %f1
> ret i32 %cond
> @@ -134,8 +112,6 @@
> entry:
> ; CHECK-MIPS32R2: c.olt.s
> ; CHECK-MIPS32R2: movt
> -; CHECK-MIPS1: c.olt.s
> -; CHECK-MIPS1: bc1f
> %cmp = fcmp olt float %f2, %f3
> %cond = select i1 %cmp, i32 %f0, i32 %f1
> ret i32 %cond
> @@ -145,8 +121,6 @@
> entry:
> ; CHECK-MIPS32R2: c.ule.s
> ; CHECK-MIPS32R2: movf
> -; CHECK-MIPS1: c.ule.s
> -; CHECK-MIPS1: bc1t
> %cmp = fcmp ogt float %f2, %f3
> %cond = select i1 %cmp, i32 %f0, i32 %f1
> ret i32 %cond
> @@ -156,8 +130,6 @@
> entry:
> ; CHECK-MIPS32R2: c.eq.d
> ; CHECK-MIPS32R2: movt
> -; CHECK-MIPS1: c.eq.d
> -; CHECK-MIPS1: bc1f
> %tmp = load double* @d2, align 8, !tbaa !0
> %tmp1 = load double* @d3, align 8, !tbaa !0
> %cmp = fcmp oeq double %tmp, %tmp1
> @@ -169,8 +141,6 @@
> entry:
> ; CHECK-MIPS32R2: c.olt.d
> ; CHECK-MIPS32R2: movt
> -; CHECK-MIPS1: c.olt.d
> -; CHECK-MIPS1: bc1f
> %tmp = load double* @d2, align 8, !tbaa !0
> %tmp1 = load double* @d3, align 8, !tbaa !0
> %cmp = fcmp olt double %tmp, %tmp1
> @@ -182,8 +152,6 @@
> entry:
> ; CHECK-MIPS32R2: c.ule.d
> ; CHECK-MIPS32R2: movf
> -; CHECK-MIPS1: c.ule.d
> -; CHECK-MIPS1: bc1t
> %tmp = load double* @d2, align 8, !tbaa !0
> %tmp1 = load double* @d3, align 8, !tbaa !0
> %cmp = fcmp ogt double %tmp, %tmp1
>
> Modified: llvm/trunk/test/CodeGen/Mips/tls.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/tls.ll?rev=139405&r1=139404&r2=139405&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/Mips/tls.ll (original)
> +++ llvm/trunk/test/CodeGen/Mips/tls.ll Fri Sep 9 15:45:50 2011
> @@ -1,5 +1,5 @@
> -; RUN: llc -march=mipsel -mcpu=mips2 < %s | FileCheck %s -check-prefix=PIC
> -; RUN: llc -march=mipsel -mcpu=mips2 -relocation-model=static < %s \
> +; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=PIC
> +; RUN: llc -march=mipsel -relocation-model=static < %s \
> ; RUN: | FileCheck %s -check-prefix=STATIC
>
>
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
--
Bruno Cardoso Lopes
http://www.brunocardoso.cc
More information about the llvm-commits
mailing list