[llvm-commits] [llvm] r139328 - in /llvm/trunk: lib/Target/ARM/Disassembler/ARMDisassembler.cpp test/MC/Disassembler/ARM/invalid-IT-CBNZ-thumb.txt
Owen Anderson
resistor at mac.com
Thu Sep 8 15:42:49 PDT 2011
Author: resistor
Date: Thu Sep 8 17:42:49 2011
New Revision: 139328
URL: http://llvm.org/viewvc/llvm-project?rev=139328&view=rev
Log:
Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block.
Added:
llvm/trunk/test/MC/Disassembler/ARM/invalid-IT-CBNZ-thumb.txt
Modified:
llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=139328&r1=139327&r2=139328&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Thu Sep 8 17:42:49 2011
@@ -77,7 +77,7 @@
EDInstInfo *getEDInfo() const;
private:
mutable std::vector<unsigned> ITBlock;
- void AddThumbPredicate(MCInst&) const;
+ DecodeStatus AddThumbPredicate(MCInst&) const;
void UpdateThumbVFPPredicate(MCInst&) const;
};
}
@@ -422,13 +422,20 @@
// encoding, but rather get their predicates from IT context. We need
// to fix up the predicate operands using this context information as a
// post-pass.
-void ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
+MCDisassembler::DecodeStatus
+ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
// A few instructions actually have predicates encoded in them. Don't
// try to overwrite it if we're seeing one of those.
switch (MI.getOpcode()) {
case ARM::tBcc:
case ARM::t2Bcc:
- return;
+ return Success;
+ case ARM::tCBZ:
+ case ARM::tCBNZ:
+ // Some instructions are not allowed in IT blocks.
+ if (!ITBlock.empty())
+ return SoftFail;
+ break;
default:
break;
}
@@ -456,7 +463,7 @@
MI.insert(I, MCOperand::CreateReg(0));
else
MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
- return;
+ return Success;
}
}
@@ -466,6 +473,8 @@
MI.insert(I, MCOperand::CreateReg(0));
else
MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
+
+ return Success;
}
// Thumb VFP instructions are a special case. Because we share their
@@ -516,7 +525,7 @@
DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI);
if (result != MCDisassembler::Fail) {
Size = 2;
- AddThumbPredicate(MI);
+ Check(result, AddThumbPredicate(MI));
return result;
}
@@ -525,7 +534,7 @@
if (result) {
Size = 2;
bool InITBlock = !ITBlock.empty();
- AddThumbPredicate(MI);
+ Check(result, AddThumbPredicate(MI));
AddThumb1SBit(MI, InITBlock);
return result;
}
@@ -534,7 +543,7 @@
result = decodeThumb2Instruction16(MI, insn16, Address, this, STI);
if (result != MCDisassembler::Fail) {
Size = 2;
- AddThumbPredicate(MI);
+ Check(result, AddThumbPredicate(MI));
// If we find an IT instruction, we need to parse its condition
// code and mask operands so that we can apply them correctly
@@ -575,7 +584,7 @@
if (result != MCDisassembler::Fail) {
Size = 4;
bool InITBlock = ITBlock.size();
- AddThumbPredicate(MI);
+ Check(result, AddThumbPredicate(MI));
AddThumb1SBit(MI, InITBlock);
return result;
}
@@ -584,7 +593,7 @@
result = decodeThumb2Instruction32(MI, insn32, Address, this, STI);
if (result != MCDisassembler::Fail) {
Size = 4;
- AddThumbPredicate(MI);
+ Check(result, AddThumbPredicate(MI));
return result;
}
@@ -600,7 +609,7 @@
result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI);
if (result != MCDisassembler::Fail) {
Size = 4;
- AddThumbPredicate(MI);
+ Check(result, AddThumbPredicate(MI));
return result;
}
@@ -612,7 +621,7 @@
result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI);
if (result != MCDisassembler::Fail) {
Size = 4;
- AddThumbPredicate(MI);
+ Check(result, AddThumbPredicate(MI));
return result;
}
}
@@ -626,7 +635,7 @@
result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI);
if (result != MCDisassembler::Fail) {
Size = 4;
- AddThumbPredicate(MI);
+ Check(result, AddThumbPredicate(MI));
return result;
}
}
Added: llvm/trunk/test/MC/Disassembler/ARM/invalid-IT-CBNZ-thumb.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-IT-CBNZ-thumb.txt?rev=139328&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-IT-CBNZ-thumb.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-IT-CBNZ-thumb.txt Thu Sep 8 17:42:49 2011
@@ -0,0 +1,5 @@
+# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 |& grep {potentially undefined instruction encoding}
+
+# CBZ / CBNZ not allowed in IT block.
+
+0xdb 0xbf 0x42 0xbb
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