[llvm-commits] [llvm] r139285 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86ISelLowering.h lib/Target/X86/X86InstrFragmentsSIMD.td lib/Target/X86/X86InstrSSE.td test/CodeGen/Generic/promote-integers.ll
Bruno Cardoso Lopes
bruno.cardoso at gmail.com
Thu Sep 8 11:11:36 PDT 2011
A couple more comments:
> + switch (Op1.getValueType().getSimpleVT().SimpleTy) {
> + default: break;
> + case MVT::v2i64: return DAG.getNode(X86ISD::BLENDVPD, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
> + case MVT::v2f64: return DAG.getNode(X86ISD::BLENDVPD, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
> + case MVT::v4i32: return DAG.getNode(X86ISD::BLENDVPS, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
> + case MVT::v4f32: return DAG.getNode(X86ISD::BLENDVPS, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
> + case MVT::v16i8: return DAG.getNode(X86ISD::PBLENDVB, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
> + }
Although you did right in tablegen, PBLENDVB operands here are wrong.
I changed the order in r139305
> +def X86blendvpd : SDNode<"X86ISD::BLENDVPD",
> + SDTypeProfile<1, 3, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
> + SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>>;
> +def X86blendvps : SDNode<"X86ISD::BLENDVPS",
> + SDTypeProfile<1, 3, [SDTCisVT<0, v4i32>, SDTCisSameAs<0,1>,
> + SDTCisSameAs<0,2>, SDTCisSameAs<0,3>]>>;
Could you please change this to be only one node "X86blendv", and then
have tablegen match the instruction by the node type?
> +def : Pat<(X86pblendvb VR128:$src1, VR128:$src2, XMM0),
> (PBLENDVBrr0 VR128:$src1, VR128:$src2)>, Requires<[HasSSE41]>;
> +def : Pat<(X86blendvpd XMM0, VR128:$src1, VR128:$src2),
> + (BLENDVPDrr0 VR128:$src1, VR128:$src2)>, Requires<[HasSSE41]>;
> +def : Pat<(X86blendvps XMM0, VR128:$src1, VR128:$src2),
> + (BLENDVPSrr0 VR128:$src1, VR128:$src2)>, Requires<[HasSSE41]>;
Also changed it in r139305
--
Bruno Cardoso Lopes
http://www.brunocardoso.cc
More information about the llvm-commits
mailing list