[llvm-commits] [llvm] r139285 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86ISelLowering.h lib/Target/X86/X86InstrFragmentsSIMD.td lib/Target/X86/X86InstrSSE.td test/CodeGen/Generic/promote-integers.ll

[Duncan Sands]

Hi Nadav,

> Add X86-SSE4 codegen support for vector-select.

yay!

> +  switch (Op1.getValueType().getSimpleVT().SimpleTy) {
> +    default: break;
> +    case MVT::v2i64: return DAG.getNode(X86ISD::BLENDVPD, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
> +    case MVT::v2f64: return DAG.getNode(X86ISD::BLENDVPD, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
> +    case MVT::v4i32: return DAG.getNode(X86ISD::BLENDVPS, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
> +    case MVT::v4f32: return DAG.getNode(X86ISD::BLENDVPS, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
> +    case MVT::v16i8: return DAG.getNode(X86ISD::PBLENDVB, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
> +  }

If you switched on the type of the condition you would reduce the number of
cases, since you wouldn't need v2f64 or v4f32.

Ciao, Duncan.