[llvm-commits] [llvm] r139057 - in /llvm/trunk: lib/Target/X86/X86InstrCompiler.td test/CodeGen/X86/cmov.ll test/CodeGen/X86/or-address.ll

[Jakob Stoklund Olesen]

Author: stoklund
Date: Fri Sep  2 18:52:55 2011
New Revision: 139057

URL: http://llvm.org/viewvc/llvm-project?rev=139057&view=rev
Log:
Pseudo CMOV instructions don't clobber EFLAGS.

The explanation about a 0 argument being materialized as xor is no
longer valid.  Rematerialization will check if EFLAGS is live before
clobbering it.

The code produced by X86TargetLowering::EmitLoweredSelect does not
clobber EFLAGS.

This causes one less testb instruction to be generated in the cmov.ll
test case.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrCompiler.td
    llvm/trunk/test/CodeGen/X86/cmov.ll
    llvm/trunk/test/CodeGen/X86/or-address.ll

Modified: llvm/trunk/lib/Target/X86/X86InstrCompiler.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrCompiler.td?rev=139057&r1=139056&r2=139057&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrCompiler.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrCompiler.td Fri Sep  2 18:52:55 2011
@@ -349,18 +349,11 @@
 //===----------------------------------------------------------------------===//
 // Conditional Move Pseudo Instructions
 
-let Constraints = "$src1 = $dst" in {
-
-// Conditional moves
-let Uses = [EFLAGS] in {
-
 // X86 doesn't have 8-bit conditional moves. Use a customInserter to
 // emit control flow. An alternative to this is to mark i8 SELECT as Promote,
 // however that requires promoting the operands, and can induce additional
-// i8 register pressure. Note that CMOV_GR8 is conservatively considered to
-// clobber EFLAGS, because if one of the operands is zero, the expansion
-// could involve an xor.
-let usesCustomInserter = 1, Constraints = "", Defs = [EFLAGS] in {
+// i8 register pressure.
+let usesCustomInserter = 1, Uses = [EFLAGS] in {
 def CMOV_GR8 : I<0, Pseudo,
                  (outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
                  "#CMOV_GR8 PSEUDO!",
@@ -400,10 +393,7 @@
                       (X86cmov RFP80:$src1, RFP80:$src2, imm:$cond,
                                                   EFLAGS))]>;
 } // Predicates = [NoCMov]
-} // UsesCustomInserter = 1, Constraints = "", Defs = [EFLAGS]
-} // Uses = [EFLAGS]
-
-} // Constraints = "$src1 = $dst" in
+} // UsesCustomInserter = 1, Uses = [EFLAGS]
 
 
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/test/CodeGen/X86/cmov.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/cmov.ll?rev=139057&r1=139056&r2=139057&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/cmov.ll (original)
+++ llvm/trunk/test/CodeGen/X86/cmov.ll Fri Sep  2 18:52:55 2011
@@ -90,8 +90,8 @@
 ; CHECK: test4:
 ; CHECK: g_100
 ; CHECK: testb
-; CHECK: testb %al, %al
-; CHECK-NEXT: setne %al
+; CHECK-NOT: xor
+; CHECK: setne
 ; CHECK-NEXT: testb
 
 func_4.exit.i:                                    ; preds = %bb.i.i.i, %entry

Modified: llvm/trunk/test/CodeGen/X86/or-address.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/or-address.ll?rev=139057&r1=139056&r2=139057&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/or-address.ll (original)
+++ llvm/trunk/test/CodeGen/X86/or-address.ll Fri Sep  2 18:52:55 2011
@@ -47,10 +47,10 @@
 }
 
 ; CHECK: test1:
-; CHECK: 	movl	%{{.*}},   (%rdi,%rcx,4)
-; CHECK:	movl	%{{.*}},  8(%rdi,%rcx,4)
-; CHECK:	movl	%{{.*}},  4(%rdi,%rcx,4)
-; CHECK:	movl	%{{.*}}, 12(%rdi,%rcx,4)
+; CHECK: 	movl	%{{.*}},   (%[[RDI:...]],%[[RCX:...]],4)
+; CHECK:	movl	%{{.*}},  8(%[[RDI]],%[[RCX]],4)
+; CHECK:	movl	%{{.*}},  4(%[[RDI]],%[[RCX]],4)
+; CHECK:	movl	%{{.*}}, 12(%[[RDI]],%[[RCX]],4)
 
 define void @test1(i32* nocapture %array, i32 %r0, i8 signext %k, i8 signext %i0) nounwind {
 bb.nph: