[llvm-commits] [llvm] r138922 - in /llvm/trunk: lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/basic-thumb2-instructions.s test/MC/ARM/thumb-diagnostics.s
Jim Grosbach
grosbach at apple.com
Wed Aug 31 17:28:52 PDT 2011
Author: grosbach
Date: Wed Aug 31 19:28:52 2011
New Revision: 138922
URL: http://llvm.org/viewvc/llvm-project?rev=138922&view=rev
Log:
Thumb2 assembly parsing and encoding for ADD(immediate).
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
llvm/trunk/test/MC/ARM/thumb-diagnostics.s
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=138922&r1=138921&r2=138922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Aug 31 19:28:52 2011
@@ -3512,3 +3512,8 @@
(t2SBCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm,
pred:$p, cc_out:$s)>;
+// Aliases for ADD immediate without the ".w" optional width specifier.
+def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm",
+ (t2ADDri rGPR:$Rd, GPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>;
+def : t2InstAlias<"add${p} $Rd, $Rn, $imm",
+ (t2ADDri12 rGPR:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>;
Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=138922&r1=138921&r2=138922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Aug 31 19:28:52 2011
@@ -3035,6 +3035,8 @@
bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
+ // FIXME: This is all horribly hacky. We really need a better way to deal
+ // with optional operands like this in the matcher table.
// The 'mov' mnemonic is special. One variant has a cc_out operand, while
// another does not. Specifically, the MOVW instruction does not. So we
@@ -3058,13 +3060,49 @@
static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
return true;
// Register-register 'add' for thumb does not have a cc_out operand
- // when it's an ADD Rdm, SP, {Rdm|#imm} instruction.
+ // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
+ // have to check the immediate range here since Thumb2 has a variant
+ // that can handle a different range and has a cc_out operand.
if (isThumb() && Mnemonic == "add" && Operands.size() == 6 &&
static_cast<ARMOperand*>(Operands[3])->isReg() &&
static_cast<ARMOperand*>(Operands[4])->isReg() &&
static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
- static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
+ static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
+ (static_cast<ARMOperand*>(Operands[5])->isReg() ||
+ static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
return true;
+ // For Thumb2, add immediate does not have a cc_out operand for the
+ // imm0_4096 variant. That's the least-preferred variant when
+ // selecting via the generic "add" mnemonic, so to know that we
+ // should remove the cc_out operand, we have to explicitly check that
+ // it's not one of the other variants. Ugh.
+ if (isThumbTwo() && Mnemonic == "add" && Operands.size() == 6 &&
+ static_cast<ARMOperand*>(Operands[3])->isReg() &&
+ static_cast<ARMOperand*>(Operands[4])->isReg() &&
+ static_cast<ARMOperand*>(Operands[5])->isImm()) {
+ // Nest conditions rather than one big 'if' statement for readability.
+ //
+ // If either register is a high reg, it's either one of the SP
+ // variants (handled above) or a 32-bit encoding, so we just
+ // check against T3.
+ if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
+ !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) &&
+ static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
+ return false;
+ // If both registers are low, we're in an IT block, and the immediate is
+ // in range, we should use encoding T1 instead, which has a cc_out.
+ if (inITBlock() &&
+ isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
+ isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
+ static_cast<ARMOperand*>(Operands[5])->isImm0_7())
+ return false;
+
+ // Otherwise, we use encoding T4, which does not have a cc_out
+ // operand.
+ return true;
+ }
+
+
// Register-register 'add/sub' for thumb does not have a cc_out operand
// when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
// the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
@@ -3220,10 +3258,11 @@
// Some instructions, mostly Thumb, have forms for the same mnemonic that
// do and don't have a cc_out optional-def operand. With some spot-checks
// of the operand list, we can figure out which variant we're trying to
- // parse and adjust accordingly before actually matching. Reason number
- // #317 the table driven matcher doesn't fit well with the ARM instruction
- // set.
- if (shouldOmitCCOutOperand(Mnemonic, Operands)) {
+ // parse and adjust accordingly before actually matching. We shouldn't ever
+ // try to remove a cc_out operand that was explicitly set on the the
+ // mnemonic, of course (CarrySetting == true). Reason number #317 the
+ // table driven matcher doesn't fit well with the ARM instruction set.
+ if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
Operands.erase(Operands.begin() + 1);
delete Op;
Modified: llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s?rev=138922&r1=138921&r2=138922&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb2-instructions.s Wed Aug 31 19:28:52 2011
@@ -60,6 +60,34 @@
@------------------------------------------------------------------------------
+@ ADD (immediate)
+ at ------------------------------------------------------------------------------
+ itet eq
+ addeq r1, r2, #4
+ addwne r5, r3, #1023
+ addeq r4, r5, #293
+ add r2, sp, #1024
+ add r2, r8, #0xff00
+ add r2, r3, #257
+ addw r2, r3, #257
+ add r12, r6, #0x100
+ addw r12, r6, #0x100
+ adds r1, r2, #0x1f0
+
+@ CHECK: itet eq @ encoding: [0x0a,0xbf]
+@ CHECK: addeq r1, r2, #4 @ encoding: [0x11,0x1d]
+@ CHECK: addwne r5, r3, #1023 @ encoding: [0x03,0xf2,0xff,0x35]
+@ CHECK: addweq r4, r5, #293 @ encoding: [0x05,0xf2,0x25,0x14]
+@ CHECK: add.w r2, sp, #1024 @ encoding: [0x0d,0xf5,0x80,0x62]
+@ CHECK: add.w r2, r8, #65280 @ encoding: [0x08,0xf5,0x7f,0x42]
+@ CHECK: addw r2, r3, #257 @ encoding: [0x03,0xf2,0x01,0x12]
+@ CHECK: addw r2, r3, #257 @ encoding: [0x03,0xf2,0x01,0x12]
+@ CHECK: add.w r12, r6, #256 @ encoding: [0x06,0xf5,0x80,0x7c]
+@ CHECK: addw r12, r6, #256 @ encoding: [0x06,0xf2,0x00,0x1c]
+@ CHECK: adds.w r1, r2, #496 @ encoding: [0x12,0xf5,0xf8,0x71]
+
+
+ at ------------------------------------------------------------------------------
@ CBZ/CBNZ
@------------------------------------------------------------------------------
cbnz r7, #6
Modified: llvm/trunk/test/MC/ARM/thumb-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumb-diagnostics.s?rev=138922&r1=138921&r2=138922&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/thumb-diagnostics.s (original)
+++ llvm/trunk/test/MC/ARM/thumb-diagnostics.s Wed Aug 31 19:28:52 2011
@@ -134,6 +134,6 @@
@ CHECK-ERRORS: error: invalid operand for instruction
@ CHECK-ERRORS: add sp, sp, #512
@ CHECK-ERRORS: ^
-@ CHECK-ERRORS: error: invalid operand for instruction
+@ CHECK-ERRORS: error: instruction requires a CPU feature not currently enabled
@ CHECK-ERRORS: add r2, sp, #1024
-@ CHECK-ERRORS: ^
+@ CHECK-ERRORS: ^
More information about the llvm-commits
mailing list