[llvm-commits] [llvm] r138910 - in /llvm/trunk/lib/Target/ARM: ARMInstrThumb2.td Disassembler/ARMDisassembler.cpp

[Jim Grosbach]

I think r r138898 fixed the branch encoding problem. Are you still seeing issues?

-Jim

On Aug 31, 2011, at 3:00 PM, Owen Anderson wrote:

> Author: resistor
> Date: Wed Aug 31 17:00:41 2011
> New Revision: 138910
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=138910&view=rev
> Log:
> The asm parser currently selects the wrong encoding for non-conditional Thumb2 branches.  However, this exposed a number of situations where the decoder was too permissive in allowing invalid instructions to decode successful.  Specify additional fixed bits to close those gaps.
> 
> Modified:
>    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
>    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=138910&r1=138909&r2=138910&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Aug 31 17:00:41 2011
> @@ -3243,7 +3243,9 @@
>   : T2I<oops, iops, itin, opc, asm, pattern> {
>   let Inst{31-20} = op31_20{11-0};
>   let Inst{15-14} = op15_14{1-0};
> +  let Inst{13}    = 0b0;
>   let Inst{12} = op12{0};
> +  let Inst{7-0}   = 0;
> }
> 
> class T2MRS<bits<12> op31_20, bits<2> op15_14, bits<1> op12,
> @@ -3276,7 +3278,6 @@
>   bits<4> Rn;
>   let Inst{19-16} = Rn;
>   let Inst{20}    = mask{4}; // R Bit
> -  let Inst{13}    = 0b0;
>   let Inst{11-8}  = mask{3-0};
> }
> 
> 
> Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=138910&r1=138909&r2=138910&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Wed Aug 31 17:00:41 2011
> @@ -2603,17 +2603,17 @@
> 
>   unsigned pred = fieldFromInstruction32(Insn, 22, 4);
>   if (pred == 0xE || pred == 0xF) {
> -    unsigned opc = fieldFromInstruction32(Insn, 4, 2);
> +    unsigned opc = fieldFromInstruction32(Insn, 4, 28);
>     switch (opc) {
>       default:
>         return Fail;
> -      case 0:
> +      case 0xf3bf8f4:
>         Inst.setOpcode(ARM::t2DSB);
>         break;
> -      case 1:
> +      case 0xf3bf8f5:
>         Inst.setOpcode(ARM::t2DMB);
>         break;
> -      case 2:
> +      case 0xf3bf8f6:
>         Inst.setOpcode(ARM::t2ISB);
>         return Success;
>     }
> 
> 
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