[llvm-commits] [llvm] r138341 - in /llvm/trunk: lib/Target/ARM/Disassembler/ARMDisassembler.cpp test/MC/Disassembler/ARM/thumb-tests.txt

[Owen Anderson]

Author: resistor
Date: Tue Aug 23 12:51:38 2011
New Revision: 138341

URL: http://llvm.org/viewvc/llvm-project?rev=138341&view=rev
Log:
Fix decoding of Thumb2 prefetch instructions, which account for all the remaining Thumb2 decoding failures found by randomized testing so far.

Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
    llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=138341&r1=138340&r2=138341&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Tue Aug 23 12:51:38 2011
@@ -2392,9 +2392,15 @@
                               uint64_t Address, const void *Decoder) {
   DecodeStatus S = Success;
 
-  if (Inst.getOpcode() != ARM::t2PLDs) {
-    unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
-    CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
+  switch (Inst.getOpcode()) {
+    case ARM::t2PLDs:
+    case ARM::t2PLDWs:
+    case ARM::t2PLIs:
+      break;
+    default: {
+      unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
+      CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
+    }
   }
 
   unsigned Rn = fieldFromInstruction32(Insn, 16, 4);

Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt?rev=138341&r1=138340&r2=138341&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt Tue Aug 23 12:51:38 2011
@@ -292,3 +292,6 @@
 
 # CHECK: uxtb16	r9, r12, ror #16
 0x3f 0xfa 0xec 0xf9
+
+# CHECK: pldw	[r11, r12, lsl #2]
+0x3b 0xf8 0x2c 0xf0