[llvm-commits] [llvm] r138108 - in /llvm/trunk: lib/Target/ARM/ARMInstrThumb.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/basic-thumb-instructions.s test/MC/ARM/thumb-diagnostics.s
Jim Grosbach
grosbach at apple.com
Fri Aug 19 15:07:46 PDT 2011
Author: grosbach
Date: Fri Aug 19 17:07:46 2011
New Revision: 138108
URL: http://llvm.org/viewvc/llvm-project?rev=138108&view=rev
Log:
Thumb assembly parsing and encoding for MUL.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
llvm/trunk/test/MC/ARM/thumb-diagnostics.s
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=138108&r1=138107&r2=138108&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Fri Aug 19 17:07:46 2011
@@ -1049,10 +1049,20 @@
// Multiply register
let isCommutable = 1 in
def tMUL : // A8.6.105 T1
- T1sItDPEncode<0b1101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
- IIC_iMUL32,
- "mul", "\t$Rdn, $Rm, $Rdn",
- [(set tGPR:$Rdn, (mul tGPR:$Rn, tGPR:$Rm))]>;
+ Thumb1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), AddrModeNone, 2,
+ IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", "$Rm = $Rd",
+ [(set tGPR:$Rd, (mul tGPR:$Rn, tGPR:$Rm))]>,
+ T1DataProcessing<0b1101> {
+ bits<3> Rd;
+ bits<3> Rn;
+ let Inst{5-3} = Rn;
+ let Inst{2-0} = Rd;
+ let AsmMatchConverter = "cvtThumbMultiply";
+}
+
+def : InstAlias<"mul${s}${p} $Rdm, $Rn", (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn,
+ pred:$p)>,
+ Requires<[IsThumb]>;
// Move inverse register
def tMVN : // A8.6.107
Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=138108&r1=138107&r2=138108&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Fri Aug 19 17:07:46 2011
@@ -145,6 +145,8 @@
const SmallVectorImpl<MCParsedAsmOperand*> &);
bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
const SmallVectorImpl<MCParsedAsmOperand*> &);
+ bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
+ const SmallVectorImpl<MCParsedAsmOperand*> &);
bool validateInstruction(MCInst &Inst,
const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
@@ -2371,6 +2373,29 @@
return true;
}
+/// cvtThumbMultiple- Convert parsed operands to MCInst.
+/// Needed here because the Asm Gen Matcher can't handle properly tied operands
+/// when they refer multiple MIOperands inside a single one.
+bool ARMAsmParser::
+cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
+ const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
+ // The second source operand must be the same register as the destination
+ // operand.
+ if (Operands.size() == 6 &&
+ ((ARMOperand*)Operands[3])->getReg() !=
+ ((ARMOperand*)Operands[5])->getReg()) {
+ Error(Operands[3]->getStartLoc(),
+ "destination register must match second source register");
+ return false;
+ }
+ ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
+ ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
+ ((ARMOperand*)Operands[4])->addRegOperands(Inst, 1);
+ Inst.addOperand(Inst.getOperand(0));
+ ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
+
+ return true;
+}
/// Parse an ARM memory expression, return false if successful else return true
/// or an error. The first token must be a '[' when called.
@@ -3220,7 +3245,8 @@
case Match_MnemonicFail:
return Error(IDLoc, "invalid instruction");
case Match_ConversionFail:
- return Error(IDLoc, "unable to convert operands to instruction");
+ // The converter function will have already emited a diagnostic.
+ return true;
case Match_RequiresITBlock:
return Error(IDLoc, "instruction only valid inside IT block");
case Match_RequiresV6:
Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=138108&r1=138107&r2=138108&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Fri Aug 19 17:07:46 2011
@@ -321,3 +321,13 @@
@ CHECK: mov r3, r4 @ encoding: [0x23,0x46]
@ CHECK: movs r1, r3 @ encoding: [0x19,0x00]
+
+
+ at ------------------------------------------------------------------------------
+@ MUL
+ at ------------------------------------------------------------------------------
+ muls r1, r2, r1
+ muls r3, r4
+
+@ CHECK: muls r1, r2, r1 @ encoding: [0x51,0x43]
+@ CHECK: muls r3, r4, r3 @ encoding: [0x63,0x43]
Modified: llvm/trunk/test/MC/ARM/thumb-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumb-diagnostics.s?rev=138108&r1=138107&r2=138108&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/thumb-diagnostics.s (original)
+++ llvm/trunk/test/MC/ARM/thumb-diagnostics.s Fri Aug 19 17:07:46 2011
@@ -62,3 +62,9 @@
@ CHECK-ERRORS: error: invalid operand for instruction
@ CHECK-ERRORS: lsls r4, r5, #32
@ CHECK-ERRORS: ^
+
+@ Mismatched source/destination operands for MUL instruction.
+ muls r1, r2, r3
+@ CHECK-ERRORS: error: destination register must match second source register
+@ CHECK-ERRORS: muls r1, r2, r3
+@ CHECK-ERRORS: ^
More information about the llvm-commits
mailing list