Author: grosbach
Date: Fri Aug 19 14:29:25 2011
New Revision: 138063
URL: http://llvm.org/viewvc/llvm-project?rev=138063&view=rev
Log:
Thumb assembly parsing and encoding for LSL(immediate).
Modified:
llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
llvm/trunk/test/MC/ARM/thumb-diagnostics.s
Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=138063&r1=138062&r2=138063&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Fri Aug 19 14:29:25 2011
@@ -970,7 +970,7 @@
// LSL immediate
def tLSLri : // A8.6.88
- T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
+ T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_31:$imm5),
IIC_iMOVsi,
"lsl", "\t$Rd, $Rm, $imm5",
[(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]> {
Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=138063&r1=138062&r2=138063&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Fri Aug 19 14:29:25 2011
@@ -2728,7 +2728,7 @@
// predicated but do have a carry-set and so weren't caught above.
if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
- Mnemonic != "umlals" && Mnemonic != "umulls") {
+ Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls") {
unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
.Case("eq", ARMCC::EQ)
.Case("ne", ARMCC::NE)
Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=138063&r1=138062&r2=138063&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Fri Aug 19 14:29:25 2011
@@ -260,3 +260,13 @@
@ CHECK: ldrsb r6, [r2, r6] @ encoding: [0x96,0x57]
@ CHECK: ldrsh r3, [r7, r1] @ encoding: [0x7b,0x5e]
+
+
+ at ------------------------------------------------------------------------------
+@ LSL (immediate)
+ at ------------------------------------------------------------------------------
+ lsls r4, r5, #0
+ lsls r4, r5, #4
+
+@ CHECK: lsls r4, r5, #0 @ encoding: [0x2c,0x00]
+@ CHECK: lsls r4, r5, #4 @ encoding: [0x2c,0x01]
Modified: llvm/trunk/test/MC/ARM/thumb-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumb-diagnostics.s?rev=138063&r1=138062&r2=138063&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/thumb-diagnostics.s (original)
+++ llvm/trunk/test/MC/ARM/thumb-diagnostics.s Fri Aug 19 14:29:25 2011
@@ -49,3 +49,14 @@
@ CHECK-ERRORS: error: writeback operator '!' expected
@ CHECK-ERRORS: ldm r2, {r5, r7}
@ CHECK-ERRORS: ^
+
+
+@ Out of range immediates for LSL instruction.
+ lsls r4, r5, #-1
+ lsls r4, r5, #32
+@ CHECK-ERRORS: error: invalid operand for instruction
+@ CHECK-ERRORS: lsls r4, r5, #-1
+@ CHECK-ERRORS: ^
+@ CHECK-ERRORS: error: invalid operand for instruction
+@ CHECK-ERRORS: lsls r4, r5, #32
+@ CHECK-ERRORS: ^