[llvm-commits] [llvm] r138059 - in /llvm/trunk: lib/Target/ARM/ARMInstrThumb.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/basic-thumb-instructions.s

[Jim Grosbach]

Author: grosbach
Date: Fri Aug 19 13:49:59 2011
New Revision: 138059

URL: http://llvm.org/viewvc/llvm-project?rev=138059&view=rev
Log:
Thumb assembly parsing and encoding for LDRB.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/test/MC/ARM/basic-thumb-instructions.s

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=138059&r1=138058&r2=138059&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Fri Aug 19 13:49:59 2011
@@ -179,11 +179,13 @@
 
 // t_addrmode_is1 := reg + imm5
 //
+def t_addrmode_is1_asm_operand : AsmOperandClass { let Name = "MemThumbRIs1"; }
 def t_addrmode_is1 : Operand<i32>,
                      ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> {
   let EncoderMethod = "getAddrModeISOpValue";
   let DecoderMethod = "DecodeThumbAddrModeIS";
   let PrintMethod = "printThumbAddrModeImm5S1Operand";
+  let ParserMatchClass = t_addrmode_is1_asm_operand;
   let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
 }
 

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=138059&r1=138058&r2=138059&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Fri Aug 19 13:49:59 2011
@@ -628,6 +628,15 @@
     int64_t Val = Mem.OffsetImm->getValue();
     return Val >= 0 && Val <= 124 && (Val % 4) == 0;
   }
+  bool isMemThumbRIs1() const {
+    if (Kind != Memory || Mem.OffsetRegNum != 0 ||
+        !isARMLowRegister(Mem.BaseRegNum))
+      return false;
+    // Immediate offset in range [0, 31].
+    if (!Mem.OffsetImm) return true;
+    int64_t Val = Mem.OffsetImm->getValue();
+    return Val >= 0 && Val <= 31;
+  }
   bool isMemThumbSPI() const {
     if (Kind != Memory || Mem.OffsetRegNum != 0 || Mem.BaseRegNum != ARM::SP)
       return false;
@@ -1000,6 +1009,13 @@
     Inst.addOperand(MCOperand::CreateImm(Val));
   }
 
+  void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
+    assert(N == 2 && "Invalid number of operands!");
+    int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue()) : 0;
+    Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
+    Inst.addOperand(MCOperand::CreateImm(Val));
+  }
+
   void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
     assert(N == 2 && "Invalid number of operands!");
     int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0;

Modified: llvm/trunk/test/MC/ARM/basic-thumb-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-thumb-instructions.s?rev=138059&r1=138058&r2=138059&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/basic-thumb-instructions.s (original)
+++ llvm/trunk/test/MC/ARM/basic-thumb-instructions.s Fri Aug 19 13:49:59 2011
@@ -210,3 +210,23 @@
         ldr r1, [r2, r3]
 
 @ CHECK: ldr	r1, [r2, r3]            @ encoding: [0xd1,0x58]
+
+
+ at ------------------------------------------------------------------------------
+@ LDRB (immediate)
+ at ------------------------------------------------------------------------------
+        ldrb r4, [r3]
+        ldrb r5, [r6, #0]
+        ldrb r6, [r7, #31]
+
+@ CHECK: ldrb	r4, [r3]                @ encoding: [0x1c,0x78]
+@ CHECK: ldrb	r5, [r6]                @ encoding: [0x35,0x78]
+@ CHECK: ldrb	r6, [r7, #31]           @ encoding: [0xfe,0x7f]
+
+
+ at ------------------------------------------------------------------------------
+@ LDRB (register)
+ at ------------------------------------------------------------------------------
+        ldrb r6, [r4, r5]
+
+@ CHECK: ldrb	r6, [r4, r5]            @ encoding: [0x66,0x5d]