[llvm-commits] [llvm] r137995 - in /llvm/trunk: lib/Target/ARM/Disassembler/ARMDisassembler.cpp test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt

[Owen Anderson]

Author: resistor
Date: Thu Aug 18 17:11:02 2011
New Revision: 137995

URL: http://llvm.org/viewvc/llvm-project?rev=137995&view=rev
Log:
Improve handling of failure and unpredictable cases for CPS, STR, and SMLA instructions.
Fixes a large class of disassembler crashes found by randomized testing.

Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
    llvm/trunk/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=137995&r1=137994&r2=137995&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Thu Aug 18 17:11:02 2011
@@ -1317,27 +1317,34 @@
   unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
   unsigned mode = fieldFromInstruction32(Insn, 0, 5);
 
+  DecodeStatus S = Success;
+
   // imod == '01' --> UNPREDICTABLE
-  if (imod == 1) return Fail;
+  // NOTE: Even though this is technically UNPREDICTABLE, we choose to
+  // return failure here.  The '01' imod value is unprintable, so there's
+  // nothing useful we could do even if we returned UNPREDICTABLE.
+
+  if (imod == 1) CHECK(S, Fail);
 
-  if (M && mode && imod && iflags) {
+  if (imod && M) {
     Inst.setOpcode(ARM::CPS3p);
     Inst.addOperand(MCOperand::CreateImm(imod));
     Inst.addOperand(MCOperand::CreateImm(iflags));
     Inst.addOperand(MCOperand::CreateImm(mode));
-    return Success;
-  } else if (!mode && !M) {
+  } else if (imod && !M) {
     Inst.setOpcode(ARM::CPS2p);
     Inst.addOperand(MCOperand::CreateImm(imod));
     Inst.addOperand(MCOperand::CreateImm(iflags));
-    return Success;
-  } else if (!imod && !iflags && M) {
+    if (mode) CHECK(S, Unpredictable);
+  } else if (!imod && M) {
     Inst.setOpcode(ARM::CPS1p);
     Inst.addOperand(MCOperand::CreateImm(mode));
-    return Success;
-  }
+    if (iflags) CHECK(S, Unpredictable);
+  } else
+    // imod == '00' && M == '0' --> UNPREDICTABLE
+    CHECK(S, Unpredictable);
 
-  return Fail;
+  return S;
 }
 
 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
@@ -2649,7 +2656,7 @@
   imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
   unsigned pred = fieldFromInstruction32(Insn, 28, 4);
 
-  if (Rn == 0xF || Rn == Rt) return Unpredictable; // UNPREDICTABLE
+  if (Rn == 0xF || Rn == Rt) CHECK(S, Unpredictable);
 
   CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
@@ -2670,7 +2677,7 @@
   imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
   unsigned pred = fieldFromInstruction32(Insn, 28, 4);
 
-  if (Rn == 0xF || Rn == Rt) return Unpredictable; // UNPREDICTABLE
+  if (Rn == 0xF || Rn == Rt) CHECK(S, Unpredictable);
 
   CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
   CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));

Modified: llvm/trunk/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt?rev=137995&r1=137994&r2=137995&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt Thu Aug 18 17:11:02 2011
@@ -1,4 +1,4 @@
-# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
+# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {potentially undefined instruction encoding}
 
 # invalid (imod, M, iflags) combination
 0x93 0x1c 0x02 0xf1