[llvm-commits] [llvm] r137892 - in /llvm/trunk/lib/Target/Mips: MipsISelLowering.cpp MipsInstrFormats.td MipsInstrInfo.td

[Bruno Cardoso Lopes]

On Wed, Aug 17, 2011 at 3:59 PM, Akira Hatanaka <ahatanak at gmail.com> wrote:
> Author: ahatanak
> Date: Wed Aug 17 17:59:46 2011
> New Revision: 137892
>
> URL: http://llvm.org/viewvc/llvm-project?rev=137892&view=rev
> Log:
> Changed definition of EXT and INS per Bruno's comments.
>
>
> Modified:
>    llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
>    llvm/trunk/lib/Target/Mips/MipsInstrFormats.td
>    llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
>
> Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=137892&r1=137891&r2=137892&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Wed Aug 17 17:59:46 2011
> @@ -558,8 +558,8 @@
>
>   return DAG.getNode(MipsISD::Ext, N->getDebugLoc(), MVT::i32,
>                      ShiftRight.getOperand(0),
> -                     DAG.getConstant(SMSize, MVT::i32),
> -                     DAG.getConstant(Pos, MVT::i32));
> +                     DAG.getConstant(Pos, MVT::i32),
> +                     DAG.getConstant(SMSize, MVT::i32));
>  }
>
>  static SDValue PerformORCombine(SDNode *N, SelectionDAG& DAG,
> @@ -613,8 +613,8 @@
>
>   return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), MVT::i32,
>                      Shl.getOperand(0),
> -                     DAG.getConstant(SMSize0, MVT::i32),
>                      DAG.getConstant(SMPos0, MVT::i32),
> +                     DAG.getConstant(SMSize0, MVT::i32),
>                      And0.getOperand(0));
>  }
>
>
> Modified: llvm/trunk/lib/Target/Mips/MipsInstrFormats.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFormats.td?rev=137892&r1=137891&r2=137892&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsInstrFormats.td (original)
> +++ llvm/trunk/lib/Target/Mips/MipsInstrFormats.td Wed Aug 17 17:59:46 2011
> @@ -102,28 +102,6 @@
>   let Inst{25-0} = addr;
>  }
>
> -// Ext and Ins
> -class ExtIns<bits<6> _funct, string instr_asm, dag Outs, dag Ins,
> -             list<dag> pattern, InstrItinClass itin>:
> -  MipsInst<Outs, Ins, !strconcat(instr_asm, "\t$dst, $src, $pos, $size"),
> -           pattern, itin>
> -{
> -  bits<5>  rt;
> -  bits<5>  rs;
> -  bits<5>  sz;
> -  bits<5>  pos;
> -  bits<6>  funct;
> -
> -  let opcode = 0x1f;
> -  let funct  = _funct;
> -
> -  let Inst{25-21} = rs;
> -  let Inst{20-16} = rt;
> -  let Inst{15-11} = sz;
> -  let Inst{10-6}  = pos;
> -  let Inst{5-0}   = funct;
> -}
> -
>  //===----------------------------------------------------------------------===//
>  //
>  //  FLOATING POINT INSTRUCTION FORMATS
>
> Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=137892&r1=137891&r2=137892&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Wed Aug 17 17:59:46 2011
> @@ -405,6 +405,19 @@
>   let shamt = 0;
>  }
>
> +// Ext and Ins
> +class ExtIns<bits<6> _funct, string instr_asm, dag ins,
> +             list<dag> pattern, InstrItinClass itin>:
> +  FR<0x1f, _funct, (outs CPURegs:$rt), ins,
> +     !strconcat(instr_asm, "\t$rt, $rs, $pos, $size"), pattern, itin> {
> +  bits<5> src;
> +  bits<5> pos;
> +  bits<5> size;
> +  let rs = src;
> +  let rd = size;
> +  let shamt = pos;
> +}
> +

If "$src = $rt" why are you encoding it in "rs" ?

>  // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
>  class Atomic2Ops<PatFrag Op, string Opstr> :
>   MipsPseudo<(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr),
> @@ -677,20 +690,19 @@
>  def RDHWR : ReadHardware;
>
>  let Predicates = [IsMips32r2] in {
> -  def Ext : ExtIns<0b000000, "ext", (outs CPURegs:$dst),
> -                   (ins CPURegs:$src, uimm16:$size, uimm16:$pos),
> -                   [(set CPURegs:$dst,
> -                     (MipsExt CPURegs:$src, immZExt5:$size, immZExt5:$pos))],
> -                   NoItinerary>;
> -  let Constraints = "$src1 = $dst" in
> -  def Ins : ExtIns<0b000100, "ins",
> -                   (outs CPURegs:$dst),
> -                   (ins CPURegs:$src, uimm16:$size, uimm16:$pos,
> -                    CPURegs:$src1),
> -                   [(set CPURegs:$dst,
> -                     (MipsIns CPURegs:$src, immZExt5:$size, immZExt5:$pos,
> -                      CPURegs:$src1))],
> -                   NoItinerary>;
> +
> +def EXT : ExtIns<0, "ext", (ins CPURegs:$rs, uimm16:$pos, uimm16:$size),
> +                 [(set CPURegs:$rt,
> +                   (MipsExt CPURegs:$rs, immZExt5:$pos, immZExt5:$size))],
> +                 NoItinerary>;
> +
> +let Constraints = "$src = $rt" in
> +def INS : ExtIns<4, "ins",
> +                 (ins CPURegs:$rs, uimm16:$pos, uimm16:$size, CPURegs:$src),
> +                 [(set CPURegs:$rt,
> +                   (MipsIns CPURegs:$rs, immZExt5:$pos, immZExt5:$size,
> +                    CPURegs:$src))],
> +                 NoItinerary>;
>  }
>
>  //===----------------------------------------------------------------------===//
>
>
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-- 
Bruno Cardoso Lopes
http://www.brunocardoso.cc