[llvm-commits] [llvm] r137804 - in /llvm/trunk: lib/Target/Mips/MipsISelLowering.cpp lib/Target/Mips/MipsISelLowering.h lib/Target/Mips/MipsInstrFormats.td lib/Target/Mips/MipsInstrInfo.td test/CodeGen/Mips/extins.ll

[Bruno Cardoso Lopes]

What about:

"CPURegs:$src1" ?

It doesn't seems to be encoded. Btw, I'm not following, what is this
operand about? It isn't part of the asm string! Can you explain?

On Wed, Aug 17, 2011 at 2:44 PM, Akira Hatanaka <ahatanak at gmail.com> wrote:
> Is this okay?
>
> On Wed, Aug 17, 2011 at 2:31 PM, Jim Grosbach <grosbach at apple.com> wrote:
>>
>> On Aug 17, 2011, at 2:15 PM, Bruno Cardoso Lopes wrote:
>>
>>> Hi,
>>>
>>> On Wed, Aug 17, 2011 at 1:54 PM, Akira Hatanaka <ahatanak at gmail.com> wrote:
>>>> Please see the attached patch.
>>>>
>>>> I couldn't find a way to have pos and size appear in the right hand
>>>> side as you suggested, but tblgen produces the correct binding.
>>>> Is this what you had in mind?
>>>
>>> No. I think you got the wrong idea. My suggestion is something like:
>>>
>>> class ExtIns<bits<6> _funct, string instr_asm, dag ins,
>>>             list<dag> pattern, InstrItinClass itin>:
>>>  FR<...> {
>>>  bits<5> pos;
>>>  bits<5> size;
>>>  bits<5> dst
>>>  let rt = dst;
>>>  let shamt = pos;
>>>  let rd = size;
>>> ....
>>> }
>>>
>>> def EXT : ExtIns<0, "ext", (ins ... uimm16:$pos, uimm16:$size),
>>>                 [(set CPURegs:$rt,
>>>                   (MipsExt CPURegs:$rs, immZExt5:$pos, immZExt5:$size))],
>>>                 NoItinerary>;
>>>
>>> This will automatically bind "pos" to "bits<5> pos", and so on.
>>> Advantage? The encoding is done automatically, no need to right custom
>>> encoding functions... Take a look at ARMInstrInfo.td for tons of
>>> examples.
>>
>> +1
>>
>> This is exactly right.
>>
>



-- 
Bruno Cardoso Lopes
http://www.brunocardoso.cc