[llvm-commits] [llvm] r137804 - in /llvm/trunk: lib/Target/Mips/MipsISelLowering.cpp lib/Target/Mips/MipsISelLowering.h lib/Target/Mips/MipsInstrFormats.td lib/Target/Mips/MipsInstrInfo.td test/CodeGen/Mips/extins.ll

[Bruno Cardoso Lopes]

Hi,

On Wed, Aug 17, 2011 at 1:54 PM, Akira Hatanaka <ahatanak at gmail.com> wrote:
> Please see the attached patch.
>
> I couldn't find a way to have pos and size appear in the right hand
> side as you suggested, but tblgen produces the correct binding.
> Is this what you had in mind?

No. I think you got the wrong idea. My suggestion is something like:

class ExtIns<bits<6> _funct, string instr_asm, dag ins,
             list<dag> pattern, InstrItinClass itin>:
  FR<...> {
  bits<5> pos;
  bits<5> size;
  bits<5> dst
  let rt = dst;
  let shamt = pos;
  let rd = size;
 ....
}

def EXT : ExtIns<0, "ext", (ins ... uimm16:$pos, uimm16:$size),
                 [(set CPURegs:$rt,
                   (MipsExt CPURegs:$rs, immZExt5:$pos, immZExt5:$size))],
                 NoItinerary>;

This will automatically bind "pos" to "bits<5> pos", and so on.
Advantage? The encoding is done automatically, no need to right custom
encoding functions... Take a look at ARMInstrInfo.td for tons of
examples.

-- 
Bruno Cardoso Lopes
http://www.brunocardoso.cc