[llvm-commits] [llvm] r137719 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

[Nadav Rotem]

Author: nadav
Date: Tue Aug 16 09:34:29 2011
New Revision: 137719

URL: http://llvm.org/viewvc/llvm-project?rev=137719&view=rev
Log:
Revert r137562 because it caused PR10674

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=137719&r1=137718&r2=137719&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Tue Aug 16 09:34:29 2011
@@ -928,13 +928,6 @@
   assert(Val.getBitWidth() == EltVT.getSizeInBits() &&
          "APInt size does not match type size!");
 
-  // In some cases the vector type is legal but the element type is illegal.
-  // In this case, promote the inserted value. The type does not need to match
-  // the vector element type. Any extra bits introduced will be
-  // truncated away.
-  if (VT.isVector())
-    EltVT = TLI.getTypeToTransformTo(*getContext(), EltVT);
-
   unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant;
   FoldingSetNodeID ID;
   AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0);