[llvm-commits] [llvm] r137551 - in /llvm/trunk: lib/Target/ARM/ARMExpandPseudoInsts.cpp test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll

[Bob Wilson]

Author: bwilson
Date: Sat Aug 13 00:14:55 2011
New Revision: 137551

URL: http://llvm.org/viewvc/llvm-project?rev=137551&view=rev
Log:
Expand VMOVQQQQ pseudo instructions.

Apparently we never added code to expand these pseudo instructions, and in
over a year, no one has noticed.  Our register allocator must be awesome!

Added:
    llvm/trunk/test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll
Modified:
    llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=137551&r1=137550&r2=137551&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Sat Aug 13 00:14:55 2011
@@ -998,6 +998,52 @@
       return true;
     }
 
+    case ARM::VMOVQQQQ: {
+      unsigned DstReg = MI.getOperand(0).getReg();
+      bool DstIsDead = MI.getOperand(0).isDead();
+      unsigned Dst0 = TRI->getSubReg(DstReg, ARM::qsub_0);
+      unsigned Dst1 = TRI->getSubReg(DstReg, ARM::qsub_1);
+      unsigned Dst2 = TRI->getSubReg(DstReg, ARM::qsub_2);
+      unsigned Dst3 = TRI->getSubReg(DstReg, ARM::qsub_3);
+      unsigned SrcReg = MI.getOperand(1).getReg();
+      bool SrcIsKill = MI.getOperand(1).isKill();
+      unsigned Src0 = TRI->getSubReg(SrcReg, ARM::qsub_0);
+      unsigned Src1 = TRI->getSubReg(SrcReg, ARM::qsub_1);
+      unsigned Src2 = TRI->getSubReg(SrcReg, ARM::qsub_2);
+      unsigned Src3 = TRI->getSubReg(SrcReg, ARM::qsub_3);
+      MachineInstrBuilder Mov0 =
+        AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
+                               TII->get(ARM::VORRq))
+                       .addReg(Dst0,
+                               RegState::Define | getDeadRegState(DstIsDead))
+                       .addReg(Src0, getKillRegState(SrcIsKill))
+                       .addReg(Src0, getKillRegState(SrcIsKill)));
+      MachineInstrBuilder Mov1 =
+        AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
+                               TII->get(ARM::VORRq))
+                       .addReg(Dst1,
+                               RegState::Define | getDeadRegState(DstIsDead))
+                       .addReg(Src1, getKillRegState(SrcIsKill))
+                       .addReg(Src1, getKillRegState(SrcIsKill)));
+      MachineInstrBuilder Mov2 =
+        AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
+                               TII->get(ARM::VORRq))
+                       .addReg(Dst2,
+                               RegState::Define | getDeadRegState(DstIsDead))
+                       .addReg(Src2, getKillRegState(SrcIsKill))
+                       .addReg(Src2, getKillRegState(SrcIsKill)));
+      MachineInstrBuilder Mov3 =
+        AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(),
+                               TII->get(ARM::VORRq))
+                       .addReg(Dst3,
+                               RegState::Define | getDeadRegState(DstIsDead))
+                       .addReg(Src3, getKillRegState(SrcIsKill))
+                       .addReg(Src3, getKillRegState(SrcIsKill)));
+      TransferImpOps(MI, Mov0, Mov3);
+      MI.eraseFromParent();
+      return true;
+    }
+
     case ARM::VLDMQIA: {
       unsigned NewOpc = ARM::VLDMDIA;
       MachineInstrBuilder MIB =

Added: llvm/trunk/test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll?rev=137551&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/2011-08-12-vmovqqqq-pseudo.ll Sat Aug 13 00:14:55 2011
@@ -0,0 +1,13 @@
+; RUN: llc %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a9 -O0
+; The following test is supposed to produce a VMOVQQQQ pseudo instruction.
+; Make sure that it gets expanded; otherwise, the compile fails when trying
+; to print the pseudo-instruction.
+
+define void @test_vmovqqqq_pseudo() nounwind ssp {
+entry:
+  %vld3_lane = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld3lane.v8i16(i8* undef, <8 x i16> undef, <8 x i16> undef, <8 x i16> zeroinitializer, i32 7, i32 2)
+  store { <8 x i16>, <8 x i16>, <8 x i16> } %vld3_lane, { <8 x i16>, <8 x i16>, <8 x i16> }* undef
+  ret void
+}
+
+declare { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.arm.neon.vld3lane.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>, i32, i32) nounwind readonly