[llvm-commits] [llvm] r137476 - in /llvm/trunk/lib/Target/ARM: ARMInstrInfo.td Disassembler/ARMDisassembler.cpp

[Owen Anderson]

Author: resistor
Date: Fri Aug 12 12:58:32 2011
New Revision: 137476

URL: http://llvm.org/viewvc/llvm-project?rev=137476&view=rev
Log:
Separate decoding for STREXD and LDREXD to make each work better.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=137476&r1=137475&r2=137476&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Fri Aug 12 12:58:32 2011
@@ -4082,7 +4082,7 @@
 let hasExtraDefRegAllocReq = 1 in
 def LDREXD: AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2),(ins addr_offset_none:$addr),
                       NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", []> {
-  let DecoderMethod = "DecodeDoubleRegExclusive";
+  let DecoderMethod = "DecodeDoubleRegLoad";
 }
 }
 
@@ -4099,7 +4099,7 @@
 def STREXD : AIstrex<0b01, (outs GPR:$Rd),
                     (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr),
                     NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []> {
-  let DecoderMethod = "DecodeDoubleRegExclusive";
+  let DecoderMethod = "DecodeDoubleRegStore";
 }
 
 def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", []>,

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp?rev=137476&r1=137475&r2=137476&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp Fri Aug 12 12:58:32 2011
@@ -135,9 +135,10 @@
                                uint64_t Address, const void *Decoder);
 static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
-static bool DecodeDoubleRegExclusive(llvm::MCInst &Inst, unsigned Insn,
+static bool DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
+                               uint64_t Address, const void *Decoder);
+static bool DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
                                uint64_t Address, const void *Decoder);
-
 
 static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
                                uint64_t Address, const void *Decoder);
@@ -2486,15 +2487,31 @@
   return true;
 }
 
-static bool DecodeDoubleRegExclusive(llvm::MCInst &Inst, unsigned Insn,
+static bool DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
+                                          uint64_t Address, const void *Decoder) {
+  unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
+  unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
+  unsigned pred = fieldFromInstruction32(Insn, 28, 4);
+
+  if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return false;
+
+  if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false;
+  if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) return false;
+  if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
+  if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false;
+
+  return true;
+}
+
+
+static bool DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
                                           uint64_t Address, const void *Decoder) {
   unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
   unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
   unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
   unsigned pred = fieldFromInstruction32(Insn, 28, 4);
 
-  if (Inst.getOpcode() == ARM::STREXD)
-    if (!DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
+  if (!DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
 
   if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return false;
   if (Rd == Rn || Rd == Rt || Rd == Rt+1) return false;